NXP Semiconductors MWCT101 S Series, Reference Manual

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• Format B: 256 IDAFs (standard IDs or extended 14-bit ID slices including IDE and
RTR)
• Format C: 512 IDAFs (standard or extended 8-bit ID slices)
Note
A chosen format is applied to all entries of the filter table. It is
not possible to mix formats within the table.
Every frame available in the FIFO has a corresponding IDHIT (Identifier Acceptance
Filter Hit Indicator) that can read in the IDHIT field from C/S word, as shown in the Rx
FIFO Structure description. Another way the CPU can obtain this information is by
accessing the RXFIR register. RXFIR[IDHIT] refers to the message at the output of the
FIFO and is valid while the IFLAG1[BUF5I] flag is asserted. The RXFIR register must
be read only before clearing the flag, which guarantees that the information refers to the
correct frame within the FIFO.
Up to 32 elements of the filter table are individually affected by the Individual Mask
Registers (RXIMRx), according to the setting of CTRL2[RFFN], allowing very powerful
filtering criteria to be defined. If MCR[IRMQ] is negated, then the FIFO filter table is
affected by RXFGMASK.
NOTE
For more information about the difference between FD and
non-FD regarding this feature, see
Table 49-3 .
49.5.8.1 Rx FIFO under DMA operation
The receive-only FIFO can support DMA. This feature is enabled by asserting both
MCR[RFEN] and MCR[DMA]. The reset value of MCR[DMA] is zero to maintain
backward compatibility with previous versions of the module that did not have the DMA
feature.
The DMA controller can read the received message by reading a message buffer structure
at the FIFO output port at the 0x80-0x8C address range.
When MCR[DMA] is asserted the CPU must not access the FIFO output port address
range. Before enabling MCR[DMA], the CPU must service the IFLAGs asserted in the
Rx FIFO region. Otherwise, these IFLAGs may show that the FIFO has data to be
serviced, and mistakenly generate a DMA request. Before disabling MCR[DMA], the
CPU must perform a clear FIFO operation.
IFLAG1[BUF5I] (Frames available in Rx FIFO) is asserted when there is at least one
frame available to be read from the FIFO. Consequently a DMA request is generated
simultaneously. Upon receiving the request, the DMA controller can read the message
Functional description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1680 NXP Semiconductors