NXP Semiconductors PXN2020, Reference Manual, Page: 186 / 1376

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
8-4 Freescale Semiconductor
8.2.1 Ports vs. General-Purpose I/O Pins
The PXN20 provides 155 individual GPIO pins, organized into 10 ports named Port A through Port K.
Port I is omitted from the series of ports. Of these ports, Ports A through J provide 16 pins each, and Port
K provides 11 pins.
The GPIO pins provide general-purpose input and output function. The GPIO pins are multiplexed with
other I/O pin functions. A pad control register (SIU_PCR) sets the multiplexing and other functions for the
pins. An input (SIU_GPDI) or output (SIU_GPDO) register controls each GPIO input and output
separately. Pins correspond to numbered control registers beginning with Port A (pin A0) and continuing
consecutively to Port K (pin K10). Registers are numbered consecutively from 0 to 154. See the following:
• Section 8.3.2.13, Pad Configuration Registers (SIU_PCR)
• Section 8.3.2.14, GPIO Pin Data Output Registers (SIU_GPDO16_19–SIU_GPDO152_154)
• Section 8.3.2.15, GPIO Pin Data Input Registers (SIU_GPDI0_3–SIU_GPDI152_154)
• Section 8.3.2.27, Parallel GPIO Pin Data Output Register 0 (SIU_PGPDO0) through
Section 8.3.2.36, Parallel GPIO Pin Data Input Register 4 (SIU_PGPDI4)
• Section 8.3.2.37, Masked Parallel GPIO Pin Data Output Register 1 (SIU_MPGPDO1).
8.3 Memory Map and Registers
This section provides a detailed description of all DSPI registers.
8.3.1 Module Memory Map
Table 8-1 is the address map for the SIU registers. All register addresses are given as an offset of the SIU
base address.
Table 8-1. SIU Memory Map
Offset from
SIU_BASE
(0xFFFE_8000)
Register Access Reset Value Section/Page
0x0000–0x0003 Reserved
0x0004 SIU_MIDR—MCU ID register R —
1
8.3.2.1/8-13
0x0008–0x000B Reserved
0x000C SIU_RSR—Reset status register R 0x8000_000U 8.3.2.2/8-14
0x0010 SIU_SRCR—System reset control register R/W 0x0800_C000 8.3.2.3/8-15
0x0014 SIU_EISR—SIU external interrupt status register R/W 0x0000_0000 8.3.2.4/8-16
0x0018 SIU_DIRER—DMA/interrupt request enable register R/W 0x0000_0000 8.3.2.5/8-17
0x001C SIU_DIRSR—DMA/interrupt request select register R/W 0x0000_0000 8.3.2.6/8-18
0x0020 SIU_OSR—Overrun status register R/W 0x0000_0000 8.3.2.7/8-19
0x0024 SIU_ORER—Overrun request enable register R/W 0x0000_0000 8.3.2.8/8-19
0x0028 SIU_IREER—External IRQ rising-edge event enable register R/W 0x0000_0000 8.3.2.9/8-20