NXP Semiconductors PXN2020, Reference Manual, Page: 837 / 1376

Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 28-15
UCPRE Prescaler Bits. The UCPRE bits select the clock divider value for the internal prescaler of unified channel.
UCPREN Prescaler Enable Bit. The UCPREN bit enables the prescaler counter.
0 Prescaler disabled (no clock) and prescaler counter is loaded with UCPRE value.
1 Prescaler enabled.
DMA Direct Memory Access Bit. The DMA bit selects whether the FLAG generation is used as an interrupt or as a
DMA request.
0 FLAG assigned to interrupt request.
1 FLAG assigned to DMA request.
IF Input Filter Bits. The IF bits control the programmable input filter, selecting the minimum input pulse width that
can pass through the filter. For output modes, these bits have no meaning.
FCK Filter Clock Select Bit. The FCK bit selects the clock source for the programmable input filter.
0 Prescaled clock.
1 Main clock.
FEN FLAG Enable Bit. The FEN bit allows the unified channel FLAG bit to generate an interrupt signal or a DMA
request signal (the type of signal to be generated is defined by the DMA bit).
0 Disable (FLAG does not generate an interrupt or DMA request).
1 Enable (FLAG generates an interrupt or DMA request).
FORCMA Force Match A Bit. For output modes, the FORCMA bit is equivalent to a successful comparison on
comparator A (except that the FLAG bit is not set). This bit is cleared by reset and is always read as 0. This
bit is valid for every output operation mode which uses comparator A, otherwise it has no effect.
0 Has no effect.
1 Force a match at comparator A.
For input modes, the FORCMA bit is not used and writing to it has no effect.
Table 28-10. EMIOS_CCR[n] Field Descriptions (continued)
Field Description
UCPRE Divide Ratio
00 1
01 2
10 3
11 4
IF
1
1
Filter latency is three clock edges.
Minimum Input Pulse Width
[FLT_CLK Periods]
0000 Bypassed
2
0001 02
0010 04
0100 08
1000 16
All others Reserved
2
The input signal is synchronized before arriving to the digital filter.