NXP Semiconductors PXN2020, Reference Manual, Page: 1059 / 1376

Inter-Integrated Circuit Bus Controller Module (I
2
C)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 32-15
32.4.1.8 Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold
the SCL low after completion of one byte transfer (9 bits). In such cases, it halts the bus clock and forces
the master clock into wait state until the slave releases the SCL line.
32.4.1.9 Clock Stretching
The clock synchronization mechanism can be used by slaves to slow the bit rate of a transfer. After the
master has driven SCL low, the slave can drive SCL low for the required period and then release it. If the
slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low
period is stretched.
32.4.2 Interrupts
32.4.2.1 General
The I
2
C uses one interrupt vector only.
32.4.2.2 Interrupt Description
There are five types of internal interrupts in the I
2
C. The interrupt service routine can determine the
interrupt type by reading the status register.
I
2
C Interrupt can be generated on:
• Arbitration lost condition (IBAL bit set)
• Byte transfer condition (TCF bit set and DMAEN bit not set)
• Address detect condition (IAAS bit set)
• No acknowledge from slave received when expected
• Bus going idle (IBB bit not set)
The I
2
C interrupt is enabled by the IBIE bit in the I
2
C control register. It must be cleared by writing 1 to
the IBIF bit in the interrupt service routine. The bus going idle interrupt needs to be additionally enabled
by the BIIE bit in the IBIC register.
Table 32-8. Interrupt Summary
Interrupt Offset Vector Priority Source Description
I
2
C Interrupt — — — IBAL, TCF,
IAAS, IBB bits in
IBSR register
When any IBAL, TCF, or IAAS bits are set an interrupt may be
caused based on arbitration lost, transfer complete or address
detect conditions. If enabled by BIIE, the deassertion of IBB can
also cause an interrupt, indicating that the bus is idle.