NXP Semiconductors PXN2020, Reference Manual, Page: 1219 / 1376

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 36-69
36.6.10.8.2 JTAG Sequence for Read Access of Memory-Mapped Resources
36.6.10.8.3 JTAG Sequence for Write Access of Memory-Mapped Resources
9 0 CAPTURE-DR

SHIFT-DR
10 0 (31) TCK clocks issued to transfer register value to TDO pin while shifting in TDI value
11 1 SHIFT-DR

EXIT1-DR (MSB of value is shifted in/out of shifter)
12 1 EXIT1-DR

UPDATE -DR (if access is write, shifter is transferred to register)
13 0 UPDATE-DR

RUN-TEST/IDLE (transfer complete - Nexus controller to reg. select state)
Table 36-42. Accessing Memory-Mapped Resources (Reads)
Step # TCLK clocks Description
1 13 Nexus Command = write to read/write access address register (RWA)
2 37 Write RWA (initialize starting read address—data input on TDI)
3 13 Nexus Command = write to read/write control/status register (RWCS)
4 37 Write RWCS (initialize read access mode and CNT value—data input on TDI)
5 13 Nexus Command = read read/write access data register (RWD)
6 37 Read RWD (data output on TDO)
7 — If CNT > 0, go back to Step #5
Table 36-43. Accessing Memory-Mapped Resources (Writes)
Step # TCLK clocks Description
1 13 Nexus Command = write to read/write access control/status register (RWCS)
2 37 Write RWCS (initialize write access mode and CNT value—data input on TDI)
3 13 Nexus Command = write to read/write address register (RWA)
4 37 Write RWA (initialize starting write address—data input on TDI)
5 13 Nexus Command = read read/write access data register (RWD)
6 37 Write RWD (data output on TDO)
7 — If CNT > 0, go back to Step #5
Table 36-41. Accessing Internal Nexus3 Registers via JTAG/OnCE (continued)
Step # TMS Pin Description