NXP Semiconductors PXN2020, Reference Manual, Page: 210 / 1376

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
8-28 Freescale Semiconductor
8.3.2.15 GPIO Pin Data Input Registers (SIU_GPDI0_3–SIU_GPDI152_154)
The definition of the SIU_GPDI0_3 register is given in Figure 8-18 . All other SIU_GPDI n registers follow
the same pattern where 4 GPDI bits are placed in a 32-bit word, with one bit per byte. Each of the 155
GPDI bits correspond to the port pin (
Table 8-20 ). Gaps exist in this memory space where the pin is not
available in the package.
The SIU_GPDI n registers are read-only registers that allow software to read the input state of an external
GPIO pin. Each byte of a register represents the input state of a single external GPIO pin. If the GPIO pin
is configured as an output, and the input buffer enable (IBE) bit is set in the associated Pad Configuration
Register, the SIU_GPDI
n register reflects the actual state of the output pin.
112_115
116_119
120_123
124_127 0x0670
0x0674
0x0678
0x067C
PH0–PH3
PH4–PH7
PH8–PH11
PH12–PH15
128_131
132_135
136_139
140_143 0x0680
0x0684
0x0688
0x068C
PJ0–PJ3
PJ4–PJ7
PJ8–PJ11
PJ12–PJ15
144_147
148_151
152_154 0x0690
0x0694
0x0698 PK0–PK3
PK4–PK7
PK8–PK10
Offset: SI 0x0800–S0x0891 Access: User read-only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 PDI0 0 0 0 0 0 0 0 PDI1
W
Reset 0 0 0 0 0 0 0 U 0 0 0 0 0 0 0 U
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 PDI2 0 0 0 0 0 0 0 PDI3
W
Reset 0 0 0 0 0 0 0 U 0 0 0 0 0 0 0 U
Figure 8-18. GPIO Pin Data Input Register 0–3 (SIU_GPDI0_3)
Table 8-19. SIU_GPDIn Field Description
Field Description
PDIn Pin Data In. This bit reflects the input state on the external GPIO pin associated with the register.
0 Signal on pin is less than or equal to V
IL
.
1 Signal on pin is greater than or equal to V
IH
.
Table 8-18. Pin Data Output Register to Pin Mapping (continued)
SIU_GPDOn Address Offset Pins