NXP Semiconductors PXN2020, Reference Manual, Page: 163 / 1376

PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 7-1
Chapter 7
Frequency Modulated Phase-Locked Loop (FMPLL)
7.1 Introduction
The frequency modulated phase-locked loop (FMPLL) module is a frequency modulated phase-locked
loop that has been optimized to generate voltage controlled oscillator (VCO) frequencies from
192 MHz – 600 MHz based on an input clock range of 4 MHz to 40 MHz. The frequency multiplication,
output dividers and the frequency modulation waveform are register-programmable through a peripheral
bus interface.
7.1.1 Block Diagram
A simplified block diagram of the FMPLL illustrates the functionality and interdependence of major
blocks (see
Figure 7-1 ). Shaded blocks represent analog circuit components that make up the core analog
portion of the FMPLL. The complete FMPLL closed-loop system contains the feedback divider (EMFD)
and output divider (ERFD), which are implemented with standard cell core logic elements. Refer to
Section 7.4.3.3, PLL Normal Mode Without FM, for details on each sub-block.
Figure 7-1. FMPLL Block Diagram
7.1.2 Features
The FMPLL has these major features:
• Input clock frequency range: 4 MHz to 40 MHz (EXTAL)
FMDAC_STEP[0:9]
D2AFM CALDAC
EXTAL
EPREDIV
PFD FILTER VCO ERFD
LOC_PLL
LOC_REF
EMFD
PLL Clock
Out
Used to create the
loss of clock reset
request and decide
which PLL mode to
switch to when
these things happen