NXP Semiconductors PXN2020, Reference Manual, Page: 862 / 1376

Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
28-40 Freescale Semiconductor
Figure 28-38. MCB Mode A1 Register Update in Up/Down Counter Mode
28.4.1.1.12 Pulse-Width and Frequency Modulation Buffered (OPWFMB) Mode
This mode provides waveforms with variable duty cycle and frequency. The internal channel counter is
automatically selected as the time base when this mode is selected. A1 register indicates the duty cycle and
B1 register the frequency. Both A1 and B1 registers are double buffered to allow smooth signal generation
when changing the registers values. It supports 0% and 100% duty cycles.
To provide smooth and consistent channel operation, this mode differs substantially from the OPWFM
mode. The main differences reside in the A1 and B1 registers update, on the delay from the A1 match to
the output pin transition, and on the range of the internal counter values, which start from 1 and go as high
as the value in the B1 register. The internal counter must not reach 0x00_0000 as consequence of a
rollover. To avoid this, the user must start OPWFMB only if the value stored at internal counter is fewer
than the value that EMIOS_CBDR register stores.
When a match on comparator A occurs the output register is set to the value of EDPOL. When a match on
comparator B occurs the output register is set to the complement of EDPOL. B1 match also causes the
internal counter to transition to 1, thus restarting the counter cycle.
Only values greater than 0x00_0001 are allowed to be written to B1 register. Loading values other than
those leads to unpredictable results.
Figure 28-39 shows the operation of the OPWFMB mode regarding output pin transitions and A1/B1
registers match events. The output pin transition occurs when the A1 or B1 match signal is deasserted,
which is indicated by the A1 match negedge detection signal. If register A1 is set to 0x00_0004, the output
pin transitions four counter periods after the cycle has started, plus one system clock cycle. In the example
shown in
Figure 28-39 the internal counter prescaler is set to two.
EMIOS_CCNTR[n]
Time
Write to A2
A1 Match A1 Match
Write to A2
0x000001
0x000005
0x000006
0x000005
A2 Value
A1 Value 0x000006
0x000005
Selected Counter = 2
A1 Load Signal
0x000006 0x000006
0x000006
Cycle n Cycle n + 1 Cycle n + 2