NXP Semiconductors PXN2020, Reference Manual, Page: 316 / 1376

Interrupts and Interrupt Controller (INTC)
PXN20 Microcontroller Reference Manual, Rev. 1
10-48 Freescale Semiconductor
Figure 10-23. NMI Connections
10.7 Dynamic Interrupt Priority Elevation
10.7.1 e200z6 Dynamic Priority Elevation
Dynamic priority elevation is not supported by the e200z6 core since the appropriate control bits are not
implemented in the HID1 register.
10.7.2 e200z0 Dynamic Priority Elevation
The e200z0 processor can be configured to support critical and/or external interrupts. Furthermore, the
processor can be configured to employ priority elevation on critical and/or external interrupt events.
Critical interrupts come from outside the platform, and are routed directly to the processor’s critical
interrupt input. External interrupts are routed through the interrupt controller. In addition to the interrupt
notification signals, various processor specific configuration flags from the e200z0 processor’s Machine
Check Register (MCR[ee,ce]) and the Hardware Implementation register (HID1) are sent to the ECSM to
determine when interrupt servicing is enabled and when high-priority elevation should be enabled. If the
e200z0 processor is configured to allow high-priority elevation on critical interrupt events, the ECSM
generates the high-priority signal upon critical interrupt detection and holds it active for the duration of
interrupt servicing, until a return from critical interrupt (rfci) is detected. If the e200z0 processor is
configured to allow high-priority elevation on external interrupt events, the ECSM generates the
high-priority signal upon external interrupt detection and holds it active for the duration of interrupt
servicing, until a return from interrupt (rfi) is detected.
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•
•
•
Interrupt
controller
DMA/Interrupt S
e
lect
EIF0
EIF1
EIF2
EIF3
EIF4
EIF15
IMUX
DMA
request
eDMA
OVF0
OVF1
OVF15
SIU_OSR
SIU_EISR
External
IRQ pins or
internal
sources
•
•
•
•
•
SIU_DIRSR
SIU
NMI1
NMI0
PC6
PC5
•
•
•
Secondary
CPU
Primary
CPU
•
•
Overrun
request
Critical
interrupt
EIF4–EIF15
DIRS0
DIRS1
DIRS0
DIRS1
DIRS0
DIRS1