NXP Semiconductors PXN2020, Reference Manual, Page: 399 / 1376

PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 14-1
Chapter 14
e200z0 Core (Z0)
14.1 Introduction
The e200 processor family is a set of CPU cores that implement low-cost versions of the Power
Architecture Book E architecture. e200 processors are designed for deeply embedded control applications
that require low cost solutions rather than maximum performance.
The e200z0 processors integrate an integer execution unit, branch control unit, instruction fetch and
load/store units, and a multi-ported register file capable of sustaining three read and two write operations
per clock. Most integer instructions execute in a single clock cycle.
The e200z0 core is a single-issue, 32-bit Power Architecture Book E VLE-only design with 32-bit general
purpose registers (GPRs). All arithmetic instructions that execute in the core operate on data in the general
purpose registers (GPRs).
NOTE
On the PXN20 family, the e200z0 core runs at half the system clock
frequency. Unless otherwise noted in this chapter, all stated clock delays are
relative to the e200z0 core clock, not the system clock.
Instead of the base Power Architecture Book E instruction set support, the e200z0 core implements only
the VLE (variable-length encoding) APU, providing improved code density. The VLE APU is further
described in
PowerPC VLE APU Definition, Version 1.01 , a separate document.
In the remainder of this document, the e200z0 core is also referred to as the “e200z0” core or “e200 core.”
14.1.1 Features
The following is a list of some of the key features of the e200z0 core:
• 32-bit Power Architecture Book E VLE-only programmer’s model
• Single issue, 32-bit CPU
• Implements the VLE APU for reduced code footprint
• In-order execution and retirement
• Precise exception handling
• Branch processing unit
— Dedicated branch address calculation adder
• Supports instruction and data access via a unified 32-bit Instruction/Data BIU (e200z0 only).
• Load/store unit