NXP Semiconductors PXN2020, Reference Manual, Page: 303 / 1376

Interrupts and Interrupt Controller (INTC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 10-35
10.4.2.1.4 Priority Comparator Submodule
The priority comparator submodule compares the highest priority output from the associated priority
arbitrator submodule with PRI in the associated INTC_CPR_PRC0 or INTC_CPR_PRC1. If the priority
comparator submodule detects that the highest priority is higher than the current priority, then it asserts the
interrupt request to the associated processor. This interrupt request to the processor asserts whether this
highest priority is raised above the value of PRI in the associated INTC_CPR_PRC0 or
INTC_CPR_PRC1, or the PRI value in the associated INTC_CPR_PRC0 or INTC_CPR_PRC1 is lowered
below this highest priority. This highest priority becomes the new priority which is written to PRI in the
associated INTC_CPR_PRC0 or INTC_CPR_PRC1 when the interrupt request to the processor is
acknowledged. Interrupt requests whose PRI
n in INTC_PSR n _ n are 0 will not cause a preemption because
their PRI n will not be higher than PRI in the associated INTC_CPR_PRC0 or INTC_CPR_PRC1.
Another function of the priority comparator subblock is to signal an update of the INTC_IACKR_PRC0
and INTC_IACKR_PRC1 with the vector number of the first interrupt that arrives that has a priority higher
than the current priority. Once the vector number and priority are captured, they cannot be superseded by
a higher priority interrupt until an update of the INTC_CPR_PRC0 or INTC_CPR_PRC1 occurs.
10.4.2.2 Last-In First-Out (LIFO)
The LIFO stores the preempted PRI values from the associated INTC_CPR_PRC0 or INTC_CPR_PRC1.
Therefore, because these priorities are stacked within the INTC, if interrupts need to be enabled during the
ISR, at the beginning of the interrupt exception handler the PRI value in the associated INTC_CPR_PRC0
or INTC_CPR_PRC1 does not need to be loaded from the associated INTC_CPR_PRC0 or
INTC_CPR_PRC1 and stored onto the context stack. Likewise, at the end of the interrupt exception
handler, the priority does not need to be loaded from the context stack and stored into the associated
INTC_CPR_PRC0 or INTC_CPR_PRC1.
The PRI value in the associated INTC_CPR_PRC0 or INTC_CPR_PRC1 is pushed onto the LIFO when
the associated INTC_IACKR_PRC0 or INTC_IACKR_PRC1 is read in software vector mode or when the
interrupt acknowledge signal from the associated processor is asserted in hardware vector mode. The
priority is popped into PRI in the associated INTC_CPR_PRC0 or INTC_CPR_PRC1 when the associated
INTC_EOIR_PRC0 or INTC_EOIR_PRC1 is written.
Although the INTC supports 16 priorities, an ISR executing with PRI in the INTC_CPR_PRC0 or
INTC_CPR_PRC1 equal to 15 will not be preempted. Therefore, the LIFO supports the stacking of 15
priorities. However, the LIFO is only 14 entries deep. An entry for a priority of 0 is not needed because of
how pushing onto a full LIFO and popping an empty LIFO are treated. If the LIFO is pushed 15 or more
times than it is popped, the first priorities pushed are overwritten. A priority of 0 would be an overwritten
priority. However, the LIFO will pop 0s if it is popped more times than pushed. Therefore, although a
priority of 0 was overwritten, it is regenerated with the popping of an empty LIFO.
The LIFO is not memory mapped.