NXP Semiconductors PXN2020, Reference Manual, Page: 858 / 1376

Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
28-36 Freescale Semiconductor
• Internal counter clearing on match start (MODE[0:6] = 001_000b)
— External clock is selected if MODE[6] is set. In this case the internal counter clears as soon as
the match signal occurs. The channel FLAG is set at the same time the match occurs. Note that
by having the internal counter cleared as soon as the match occurs and incremented at the next
input event a shorter zero count is generated. See
Figure 28-57 and Figure 28-59 .
— Internal clock source is selected if MODE[6] is cleared. In this case the counter clears as soon
as the match signal occurs. The channel FLAG is set at the same time the match occurs. At the
next prescaler tick after the match the internal counter remains at zero and only resumes
counting on the following tick. See
Figure 28-57 and Figure 28-60 .
• Internal counter clearing on match end (MODE[0:6] = 001_001b)
— External clock is selected if MODE[6] is set. In this case the internal counter clears when the
match signal is asserted and the input event occurs. The channel FLAG is set at the same time
the counter is cleared. See
Figure 28-57 and Figure 28-61 .
— Internal clock source is selected if MODE[6] is cleared. In this case the internal counter clears
when the match signal is asserted and the prescaler tick occurs. The channel FLAG is set at the
same time the counter is cleared. See
Figure 28-57 and Figure 28-61 .
NOTE
If internal clock source is selected and the prescaler of the internal counter
is set to 1, the MC mode behaves the same way even in Clear on Match Start
or Clear on Match End sub-modes.
When in up/down count mode (MODE[0:6] = 001_01bb), a match between the internal counter and
register A1 sets the FLAG and changes the counter direction from increment to decrement. A match
between register B1 and the internal counter changes the counter direction from decrement to increment
and sets the FLAG only if MODE[5] bit is set.
Only values other than 0x00_0000 must be written into register A. Loading 0x00_0000 leads to
unpredictable results.
Updates on register A or the counter in MC mode may cause loss of match in the current cycle if the
transfer occurs near the match. In this case, the counter may roll over and resume operation in the next
cycle.
Figure 28-33 and Figure 28-34 show how the Unified Channel can be used as a modulus counter in up
mode and up/down mode, respectively.