NXP Semiconductors PXN2020, Reference Manual, Page: 279 / 1376

Interrupts and Interrupt Controller (INTC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 10-11
NOTE
A store to raise the PRI field which closely precedes an access to a shared
resource can result in a non-coherent access to that resource unless an
mbar
or msync followed by an isync sequence of instructions is executed between
the accesses. An mbar or msync instruction is also necessary after
accessing the resource but before lowering the PRI field. Refer to
Section 10.5.5.2, Ensuring Coherency, for example code to ensure
coherency.
Table 10-4. PRI Values
PRI Meaning
1111 Priority 15—highest priority
1110 Priority 14
1101 Priority 13
1100 Priority 12
1011 Priority 11
1010 Priority 10
1001 Priority 9
1000 Priority 8
0111 Priority 7
0110 Priority 6
0101 Priority 5
0100 Priority 4
0011 Priority 3
0010 Priority 2
0001 Priority 1
0000 Priority 0—lowest priority