NXP Semiconductors PXN2020, Reference Manual, Page: 322 / 1376

General-Purpose Static RAM (SRAM)
PXN20 Microcontroller Reference Manual, Rev. 1
11-4 Freescale Semiconductor
The intent of this is to detect all odd-bit failures, all two-bit failures, some three-bit failures, and some
multi-bit failures, with regard to IEC 61508-7 A.5.6.
NOTE
The SRAM does not detect all errors greater than 2 bits.
Internal SRAM write operations are performed on the following byte boundaries:
• 1 byte (0:7 bits)
• 2 bytes (0:15 bits)
• 4 bytes or 1 word (0:31 bits)
• 8 bytes or 2 words (0:63 bits)
If the entire 64 data bits are written to SRAM, no read operation is performed and the ECC is calculated
across the 64-bit data bus. The 8-bit ECC is appended to the data segment and written to SRAM.
If the write operation is less than the entire 64-bit data width (1-, 2-, or 4-byte segment), the following
occurs:
1. The ECC mechanism checks the entire 64-bit data bus for errors, detecting and either correcting or
flagging errors.
2. The write data bytes (1-, 2-, or 4-byte segment) are merged with the corrected 64 bits on the data
bus.
3. The ECC is then calculated on the resulting 64 bits formed in the previous step.
4. The 8-bit ECC result is appended to the 64 bits from the data bus, and the 72-bit value is then
written to SRAM.
11.5.1 Access Timing
The system bus is a two-stage pipelined bus, which makes the timing of any access dependent on the access
during the previous clock. Table 14-3 lists the various combinations of read and write operations to SRAM
and the number of wait states used for the each operation. The table columns contain the following
information:
Current operation Lists the type of SRAM operation executing currently
Previous operation Lists the valid types of SRAM operations that can precede the current SRAM
operation (valid operation during the preceding clock)
Wait states Lists the number of wait states (bus clocks) the operation requires which depends
on the combination of the current and previous operation