General-Purpose Static RAM (SRAM)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
11-3
11.1.3
Modes of Operation
There are two main operating modes of DSPI: normal mode and sleep mode. These modes are briefly
described in this section.
11.1.3.1
Normal (Functional) Mode
Normal mode allows for reads and writes of the SRAM memory arrays.
11.1.3.2
Sleep Mode
The size of RAM retained during Sleep mode is controlled in the CRP, in CRP_PSCR[RAMSEL[2:0]].
Sleep mode preserves the contents of the portion of the memory during low-power sleep mode. See
Chapter 6, Clocks, Reset, and Power (CRP).
11.2
External Signal Description
There are no external signals associated with the SRAM.
11.3
Memory Map and Registers
There are no control or status registers directly associated with the SRAM module, although
error-correcting code (ECC) registers are provided in the error correction status module (ECSM). See
Chapter 19, Error Correction Status Module (ECSM),
for more information.
The RAM is implemented in two blocks to allow the many masters on the device to access this memory
without significantly blocking between the masters. This is necessary since some masters such as the MLB
DIM and the FlexRay controller perform significant number of RAM accesses while still allowing the
main CPU and IOP to access RAM space.
11.4
Functional Description
ECC checks are performed during the read portion of an SRAM ECC read/write (R/W) operation, and
ECC calculations are performed during the write portion of a read/write (R/W) operation. Because the
ECC bits can contain random data after the device is powered on, you must initialize the SRAM by
executing 64-bit write instructions to the entire SRAM. For more information, refer to
Initialization and Application Information.
11.5
SRAM ECC Mechanism
The SRAM ECC detects the following conditions and produces the following results:
•
Detects and corrects all 1-bit errors
•
Detects and flags all 2-bit errors as non-correctable errors
•
Detects 72-bit reads (64-bit data bus plus the 8-bit ECC) that return all zeros or all ones, asserts an
error indicator on the bus cycle, and sets the error flag
Summary of Contents for PXN2020
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