NXP Semiconductors PXN2020, Reference Manual, Page: 1301 / 1376

Memory Map
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor A-43
0x0004 SWT_IR – SWT interrupt register R/W 0x0000_0000 20.3.2.2/20-4
0x0008 SWT_TO – SWT time-out register R/W 0x0002_7FFF 20.3.2.3/20-4
0x000C SWT_WN – SWT window register R/W 0x0000_0000 20.3.2.4/20-5
0x0010 SWT_SR – SWT service register R/W 0x0000_0000 20.3.2.5/20-6
0x0014 SWT_CO – SWT counter output register R 0x0000_0000 20.3.2.6/20-6
0x0018 SWT_SK – SWT service key register R/W 0x0000_0000 20.3.2.7/20-7
0x001C– 0x3FFF Reserved
0xFFF3_C000
STM
Chapter 21, System Timer Module (STM)
0x0000 STM_CR – STM control register R/W 0x0000_0000 21.3.2.1/21-3
0x0004 STM_CNT – STM counter value R/W 0x0000_0000 21.3.2.2/21-3
0x0008–0x000F Reserved
0x0010 STM_CCR0 – STM channel 0 control register R/W 0x0000_0000 21.3.2.3/21-4
0x0014 STM_CIR0 – STM channel 0 interrupt register R/W 0x0000_0000 21.3.2.4/21-4
0x0018 STM_CMP0 – STM channel 0 compare register R/W 0x0000_0000 21.3.2.5/21-5
0x001C Reserved
0x0020 STM_CCR1 – STM channel 1 control register R/W 0x0000_0000 21.3.2.3/21-4
0x0024 STM_CIR1 – STM channel 1 interrupt register R/W 0x0000_0000 21.3.2.4/21-4
0x0028 STM_CMP1 – STM channel 1 compare register R/W 0x0000_0000 21.3.2.5/21-5
0x002C Reserved
0x0030 STM_CCR2 – STM channel 2 control register R/W 0x0000_0000 21.3.2.3/21-4
0x0034 STM_CIR2 – STM channel 2 interrupt register R/W 0x0000_0000 21.3.2.4/21-4
0x0038 STM_CMP2 – STM channel 2 compare register R/W 0x0000_0000 21.3.2.5/21-5
0x003C Reserved
0x0040 STM_CCR3 – STM channel 3 control register R/W 0x0000_0000 21.3.2.3/21-4
0x0044 STM_CIR3 – STM channel 3 interrupt register R/W 0x0000_0000 21.3.2.4/21-4
0x0048 STM_CMP3 – STM channel 3 compare register R/W 0x0000_0000 21.3.2.5/21-5
0x004C–0x3FFF Reserved
0xFFF4_0000
ECSM
Chapter 19, Error Correction Status Module (ECSM)
0x0000–0x0023 Reserved
0x0024 FBOMCR—FEC burst optimization master control register R/W 0x0000_0000 19.2.2.1/19-3
Table A-4. PXN20 Detailed Register Map (continued)
Address Offset
from Module Base
Register Access
1
Reset Value
2
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