NXP Semiconductors PXN2020, Reference Manual, Page: 1159 / 1376

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 36-9
36.4.1 NDI Functional Description
The NDI block is implemented by integrating the following blocks on the PXN20:
• Nexus Port Controller Block
• Nexus e200z6 Development Interface (OnCE and subblocks)
• Nexus e200z0 Development Interface (OnCE and subblocks)
Refer to the block guides for more information about these blocks. Note that the TAP controller logic, reset
logic, and some miscellaneous logic are duplicated in all these blocks.
36.4.1.1 Enabling Nexus Clients for TAP Access
Once the NDI is out of the reset state, the loading of a specific instruction in the JTAG controller (JTAGC)
block is required to grant the NDI ownership of the TAP. Each Nexus client has its own JTAGC instruction
opcode for ownership of the TAP, granting that client the means to read/write its registers. The JTAGC
instruction opcode for each Nexus client is shown in
Table 35-2 . Once the JTAGC opcode for a client has
been loaded, the client is enabled by loading its NEXUS-ENABLE instruction. Opcodes for all other
instructions supported by Nexus clients can be found in the relevant sections of this chapter.
Details for accessing the NPC registers is covered in Section 36.5.5.2.3, NPC IEEE 1149.1-2001 (JTAG)
TAP.
36.4.1.2 TAP Sharing
Each of the individual Nexus blocks on the MCU implements a TAP controller for accessing its registers.
The JTAGC controls the ownership of the TAP so that the interface to all of these individual TAP
controllers appears to be a single port from outside the device. Once a Nexus client has been granted
ownership of the TAP, any data input via TDI and TMS is passed to the selected TAP controller, and any
TDO output from the selected TAP controller is sent back to the JTAGC to be output on the pins. The
JTAGC regains control of the JTAG port during the UPDATE-DR state if the PAUSE-DR state was
entered. Auxiliary TAP controllers are held in RUN-TEST/IDLE while they are inactive.
36.4.1.3 Configuring the NDI for Nexus Messaging
The NDI is placed in disabled mode upon exit of power-on reset. If message transmission via the auxiliary
port is desired, a write to the port configuration register (PCR) located in the NPC is then required to enable
the NDI and select the mode of operation. Asserting MCKO_EN in the PCR places the NDI in enabled
mode and enables MCKO. The frequency of MCKO is selected by writing the MCKO_DIV field.
Asserting the FPM bit selects full-port mode.
NOTE
Reduced-port mode is not supported. The FPM bit in the PCR must be set
when configuring the NDI.
3
See Section 36.6.8 for a detailed description of the e200z6 Nexus registers.
4
See Section 36.7.7 for a detailed description of the e200z0 Nexus registers.