NXP Semiconductors PXN2020, Reference Manual, Page: 310 / 1376

Interrupts and Interrupt Controller (INTC)
PXN20 Microcontroller Reference Manual, Rev. 1
10-42 Freescale Semiconductor
10.5.5 Priority Ceiling Protocol
10.5.5.1 Elevating Priority
The PRI field in INTC current priority register (INTC_CPR_PRC0 or INTC_CPR_PRC1) is elevated in
the OSEK PCP to the ceiling of all of the priorities of the ISRs that share a resource. This protocol allows
coherent accesses of the ISRs to that shared resource.
For example, ISR1 has a priority of 1, ISR2 has a priority of 2, and ISR3 has a priority of 3. They all share
the same resource. Before ISR1 or ISR2 can access that resource, they must raise the PRI value in
INTC_CPR_PRC
n to 3, the ceiling of all of the ISR priorities. After they release the resource, the PRI
value in INTC_CPR_PRC n can be lowered. If they do not raise their priority, ISR2 can preempt ISR1, and
ISR3 can preempt ISR1 or ISR2, possibly corrupting the shared resource. Another possible failure
mechanism is deadlock if the higher priority ISR needs the lower priority ISR to release the resource before
it can continue, but the lower priority ISR cannot release the resource until the higher priority ISR
completes and execution returns to the lower priority ISR.
Using the PCP instead of disabling processor recognition of all interrupts eliminates the time when
accessing a shared resource that all higher priority interrupts are blocked. For example, while ISR3 cannot
preempt ISR1 while it is accessing the shared resource, all of the ISRs with a priority higher than 3 can
preempt ISR1.
10.5.5.2 Ensuring Coherency
Non-coherent accesses to a shared resource can occur. As an example, ISR1 and ISR2 both share a
resource. ISR1 has a lower priority, therefore it executes and then writes the new PRI value to the current
priority register (INTC_CPR_PRC
n ). The next instruction writes a value to a shared coherent data block.
If INTC asserts the ISR2 interrupt request to the processor just before or at the same time as the first ISR1
write, it is possible for both the ISR1 and ISR2 writes to execute while the processor responds to the INTC
request, discards the transactions, and flushes the processing pipeline. However, ISR2 cannot access the
data block coherently because the data block is now corrupted.
OSEK uses the GetResource and ReleaseResource system services to manage access to a shared resource.
To prevent corrupting a coherent data block, use the following code to modify the PRI in
INTC_CPR_PRC
n . Interrupts must be disabled before executing the following GetResource code
sequence:
disable processor recognition of interrupts
PRI modification
enable processor recognition of interrupts
10.5.5.2.1 Raised Priority Preserved
Before the instruction after the GetResource system service executes, all pending transactions have
completed. These pending transactions can include an ISR for a peripheral or software settable interrupt
request whose priority was equal to or lower than the raised priority. Also, during the epilog of the interrupt
exception handler for this preempting ISR, the raised priority has been restored from the LIFO to PRI in
INTC_CPR. The shared coherent data block now can be accessed coherently.
Figure 10-22 shows the