NXP Semiconductors PXN2020, Reference Manual, Page: 1220 / 1376

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
36-70 Freescale Semiconductor
36.7 e200z0 Class 2+ Nexus Module ()
The module provides real-time development capabilities for the device core in compliance with
the IEEE-ISTO Nexus 5001-2003 standard. This module provides development support capabilities
without requiring the use of address and data pins for internal visibility.
A portion of the pin interface (the JTAG port) is also shared with the OnCE / Nexus 1 unit. The IEEE-ISTO
5001-2003 standard defines an extensible auxiliary port that is used in conjunction with the JTAG port in
e200z0 processors.
36.7.1 Introduction
This section defines the auxiliary pin functions, transfer protocols and standard development features of
the module. The development features supported are Program trace, watchpoint messaging,
ownership trace, and read/write access via the JTAG interface. The module also supports two
class four features: Watchpoint Triggering and Processor Overrun Control.
NOTE
Throughout this section references are made to the auxiliary port and its
specific signals, such as MCKO, MSEO[1:0], MDO[11:0], and others. In
actual use, the device NPC module arbitrates the access of the single
auxiliary port. To simplify the description of the function of the
module, the interaction of the NPC is omitted and the behavior described as
if the module has its own dedicated auxiliary port.