NXP Semiconductors PXN2020, Reference Manual, Page: 577 / 1376

Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 25-11
• LATE_COL – IEEE_T_LCOL
• COL_RETRY_LIM – IEEE_T_EXCOL
• XFIFO_UN – IEEET_MACERR
Offset: FE 0x0004 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R HB
ERR
BABR BABT GRA TXF TXB RXF RXB MII
EB
ERR
LC RL UN 0 0 0
W w1c
1
1
“w1c” signifies the bit is cleared by writing 1 to it.
w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 25-2. Ethernet Interrupt Event Register (EIR)
Table 25-4. EIR Field Descriptions
Field Description
HBERR Heartbeat error. This interrupt indicates that HBC is set in the TCR register and that the COL input was not
asserted within the Heartbeat window following a transmission.
BABR Babbling receive error. This bit indicates a frame was received with length in excess of RCR[MAX_FL] bytes.
BABT Babbling transmit error. This bit indicates that the transmitted frame length has exceeded RCR[MAX_FL]
bytes. This condition is usually caused by a frame that is too long being placed into the transmit data buffers.
Truncation does not occur.
GRA Graceful stop complete. This interrupt is asserted for one of three reasons. Graceful stop means that the
transmitter is put into a pause state after completion of the frame currently being transmitted.
• A graceful stop, which was initiated by the setting of the TCR[GTS] bit is now complete.
• A graceful stop, which was initiated by the setting of the TCR[TFC_PAUSE] bit is now complete.
• A graceful stop, which was initiated by the reception of a valid full duplex flow control “pause” frame is
now complete.
TXF Transmit frame interrupt. This bit indicates that a frame has been transmitted and that the last corresponding
buffer descriptor has been updated.
TXB Transmit buffer interrupt. This bit indicates that a transmit buffer descriptor has been updated.
RXF Receive frame interrupt. This bit indicates that a frame has been received and that the last corresponding
buffer descriptor has been updated.
RXB Receive buffer interrupt. This bit indicates that a receive buffer descriptor has been updated that was not the
last in the frame.
MII MII interrupt. This bit indicates that the MII has completed the data transfer requested.
EBERR Ethernet bus error. This bit indicates that a system bus error occurred when a DMA transaction was
underway. When the EBERR bit is set, ECR[ETHER_EN] is cleared, halting frame processing by the FEC.
When this occurs, software must ensure that the FIFO controller and DMA are also soft reset.