NXP Semiconductors PXN2020, Reference Manual, Page: 1025 / 1376

Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 31-35
If the ILT bit is 1, the idle character detection starts after the reception of the last stop bit.
31.4.5.3.9 CPU Controlled SCI Data Frame Reception
This section describes the reception process when the receiver is in the run state.
When the required number of frame bits have been received, the payload bits of the received frame are
transferred into eSCI SCI Data Register (eSCI_SDR) if the RDRF flag is 0. The receive data register full
flag RDRF in eSCI Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set. If the receive interrupt enable
bit RIE in the eSCI Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set, the RDRF interrupt request
is generated.
If an idle character has been detected, the IDLE flag in the eSCI Interrupt Flag and Status Register 1
(eSCI_IFSR1) is set. If the idle line interrupt enable bit ILIE in the eSCI Control Register 1 (eSCI_CR1)
is set, the IDLE interrupt request is generated.
If any of the receiver errors described in Section 31.4.5.4, Reception Error Reporting, have been occurred,
that corresponding flags are set.
If the application disabled the receiver by clearing the receiver enable bit RE in the eSCI Interrupt Flag
and Status Register 1 (eSCI_IFSR1), the current frame is discarded and no flags are updated.
31.4.5.3.10 DMA Controlled SCI Data Frames Reception
In this mode, the eSCI module controls the reception of SCI data frames automatically and utilizes the
connected DMA channels.
Figure 31-31 shows an overview of the DMA-controlled SCI data frame
reception. The RX DMA channel is used to transfer the received frame data into the memory.
When new data is received, the module generates the receive DMA request and the DMA controller
retrieves the provided data from the eSCI SCI Data Register (eSCI_SDR). The read access from the low
byte of the eSCI SCI Data Register (eSCI_SDR) signals the end of the DMA cycle for the current data and
triggers the reception of new data. The read access from the eSCI SCI Data Register (eSCI_SDR) triggers
no internal action
The application request the eSCI module to enter this mode by setting the RXDMA bit in the eSCI Control
Register 2 (eSCI_CR2). From this point in time, the module start the generation of DMA requests and
frame transmission and reception. Before entering this mode, the application should perform the following
actions:
1. Configure the module for SCI mode.
2. Enable the receiver by setting RE in eSCI Control Register 1 (eSCI_CR1) to 1.
3. Set up the DMA controller channel.