FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
26-146
Freescale Semiconductor
The increment condition for each slot status counter consists of two parts, the frame related condition part
and the slot related condition part. The internal slot status counter SSCR
n
_INT is incremented if at least
one of the conditions is fulfilled:
1. frame related condition:
•
(SSCCR
n
.VFR | SSCCR
n
.SYF | SSCCR
n
.NUF | SSCCR
n
.SUF) // count on frame condition = 1;
and
•
((~SSCCR
n
.VFR |
vSS!ValidFrame
) & // valid frame restriction
(~SSCCR
n
.SYF |
vRF!Header!SyFIndicator
) & // sync frame indicator restriction
(~SSCCR
n
.NUF | ~
vRF!Header!NFIndicator
) & // null frame indicator restriction
(~SSCCR
n
.SUF |
vRF!Header!SuFIndicator
)) // startup frame indicator restriction = 1;
NOTE
The indicator bits SYF, NUF, and SUF are valid only when a valid frame
was received. Thus it is required to set the VFR always, whenever count on
frame condition is used.
2. slot related condition:
•
((SSCCR
n
.STATUSMASK[3] &
vSS!ContentError
) | // increment on content error
(SSCCR
n
.STATUSMASK[2] &
vSS!SyntaxError
) | // increment on syntax error
(SSCCR
n
.STATUSMASK[1] &
vSS!BViolation
) | // increment on boundary violation
(SSCCR
n
.STATUSMASK[0] &
vSS!TxConflict
)) // increment on transmission conflict = 1;
If the slot status counter is in single cycle mode (SSCCR
n
.MCY = 0), the internal slot status counter
SSCR
n
_INT is reset at each cycle start. If the slot status counter is in the multicycle mode
(SSCCR
n
.MCY = 1), the counter is not reset and incremented, until the maximum value is reached.
26.6.18.5 Message Buffer Slot Status Field
Each individual message buffer and each FIFO message buffer provides a slot status field, which provides
the information shown in
for the static/dynamic slot. The update conditions for the slot status
field depend on the message buffer type. Refer to the Message Buffer Update Sections in
Individual Message Buffer Functional Description.
26.6.19 System Bus Access
This section provides a description of the system bus accesses performed by the controller.
All FlexRay memory data located in the system memory are accessed via the system bus. There are two
types of failures that can occur during the system bus access, the system bus illegal address access and the
system bus access timeout.
The behavior of the controller after the occurrence of a system bus failure is defined by the SBFF bit in
the
Summary of Contents for PXN2020
Page 1: ...PXN20 Microcontroller Reference Manual Devices Supported PXN2020 PXN2120 PXN20RM Rev 1 06 2011...
Page 42: ...PXN20 Microcontroller Reference Manual Rev 1 lxiv Freescale Semiconductor...
Page 64: ...Introduction PXN20 Microcontroller Reference Manual Rev 1 1 22 Freescale Semiconductor...
Page 112: ...Signal Description PXN20 Microcontroller Reference Manual Rev 1 3 44 Freescale Semiconductor...
Page 118: ...Resets PXN20 Microcontroller Reference Manual Rev 1 4 6 Freescale Semiconductor...
Page 372: ...e200z6 Core Z6 PXN20 Microcontroller Reference Manual Rev 1 13 8 Freescale Semiconductor...
Page 412: ...e200z0 Core Z0 PXN20 Microcontroller Reference Manual Rev 1 14 14 Freescale Semiconductor...
Page 821: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 Freescale Semiconductor 27 49...
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Page 1376: ...Memory Map PXN20 Microcontroller Reference Manual Rev 1 A 118 Freescale Semiconductor...