NXP Semiconductors PXN2020, Reference Manual, Page: 165 / 1376

Frequency Modulated Phase-Locked Loop (FMPLL)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 7-3
7.3.2 Register Descriptions
This section lists the FMPLL registers in address order and describes the registers and their bit fields.
7.3.2.1 FMPLL Synthesizer Status Register (SYNSR)
Table 7-1. FMPLL Memory Map
Offset from
FMPLL_BASE_ADDR
(0xFFFF_0000)
Register Access Reset Value Section/Page
0x0000 Reserved
0x0004 SYNSR—FMPLL synthesizer status register R/W 0x0000_0000 7.3.2.1/7-3
0x0008 ESYNCR1—FMPLL enhanced synthesizer control register 1 R/W 0x8000_0030 7.3.2.2/7-5
0x000C ESYNCR2—FMPLL enhanced synthesizer control register 2 R/W 0x0000_0003 7.3.2.3/7-7
0x0010–0x0014 Reserved
Offset: FMPLL_BAS 0x0004 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0 0 0 0 0 LOLF LOC MODE
PLL
SEL
PLL
REF
LOCKS LOCK LOCF
CAL
DONE
CAL
PASS
W w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 7-2. FMPLL Synthesizer Status Register (SYNSR)
Table 7-2. SYNSR Register Field Descriptions
Field Description
LOLF Loss- of-Lock Flag. This bit provides the interrupt request flag. To clear the flag, write a 1 to the bit. Writing 0 has
no effect. This flag will not be set, and an interrupt will not be requested, if the loss-of-lock condition was caused
by a system reset, enabling of frequency modulation, or a write to the ESYNCR1 which modifies the
ESYNCR1[EMFD] bits. If the flag is set due to a system failure, writing the ESYNCR1[EMFD] bits or enabling FM
does not clear the flag. Assert reset to clear the flag. If lock is reacquired, the bit remains set until either a write
1 or reset is asserted.
0 Interrupt service not requested.
1 Interrupt service requested.