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Flash Memory Array and Control
PXN20 Microcontroller Reference Manual, Rev. 1
12-14
Freescale Semiconductor
12.3.2.5
Low/Mid Address Space Block Select Register (LMS)
The Low/Mid Address Space Block Select Register (LMS) provides a means to select blocks to be
operated on during erase.
The LMS register is shown in
.
Offset: FLASH_REG 0x000C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
SLE
0
0
0
0
0
0
0
0
0
0
SS
LOCK
0
0
SM
LOCK
W
Reset
0
0
0
0
0
0
0
0
0
0
0
1*
0
0
1*
1*
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
0
SLLOCK
W
Reset
0
0
0
0
0
0
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
Figure 12-6. Secondary Low/Mid Address Block Locking Register (SLL)
Table 12-7. SLL Field Descriptions
Field
Description
SLE
Secondary Low/Mid Address Lock Enable. This bit is used to enable the Lock registers (SSLOCK,
SMLOCK, and SLLOCK) to be set or cleared by register writes. This bit is a status bit only, and may not
be written or cleared, and the reset value is 0. The method to set this bit is to provide a password, and
if the password matches, the SLE bit is set to reflect the status of enabled, and is enabled until a reset
operation occurs. For SLE, the password 0xC3C3_3333 must be written to the SLL register
0 Secondary Low/Mid Address Locks are disabled, and cannot be modified.
1 Secondary Low/Mid Address Locks are enabled to be written.
SSLOCK
Secondary Shadow Lock. This bit is an alternative method that may be used to lock the shadow block
from programs and erases. SSLOCK has the same description as SLOCK. SSLOCK is not writable
unless SLE is high.
SMLOCK[1:0]
Secondary Mid Address Block Lock. This bit is an alternative method that may be used to lock the Mid
Address Space blocks from programs and erases. SMLOCK has the same description as MLOCK.
SMLOCK is not writable unless SLE is high.
SLLOCK[9:0]
Secondary Low Address Block Lock. This bit is an alternative method that may be used to lock the Low
Address Space blocks from programs and erases. SLLOCK has the same description as LLOCK.
SLLOCK is not writable unless SLE is high.
Summary of Contents for PXN2020
Page 1: ...PXN20 Microcontroller Reference Manual Devices Supported PXN2020 PXN2120 PXN20RM Rev 1 06 2011...
Page 42: ...PXN20 Microcontroller Reference Manual Rev 1 lxiv Freescale Semiconductor...
Page 64: ...Introduction PXN20 Microcontroller Reference Manual Rev 1 1 22 Freescale Semiconductor...
Page 112: ...Signal Description PXN20 Microcontroller Reference Manual Rev 1 3 44 Freescale Semiconductor...
Page 118: ...Resets PXN20 Microcontroller Reference Manual Rev 1 4 6 Freescale Semiconductor...
Page 372: ...e200z6 Core Z6 PXN20 Microcontroller Reference Manual Rev 1 13 8 Freescale Semiconductor...
Page 412: ...e200z0 Core Z0 PXN20 Microcontroller Reference Manual Rev 1 14 14 Freescale Semiconductor...
Page 821: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 Freescale Semiconductor 27 49...
Page 822: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 27 50 Freescale Semiconductor...
Page 1376: ...Memory Map PXN20 Microcontroller Reference Manual Rev 1 A 118 Freescale Semiconductor...