NXP Semiconductors PXN2020, Reference Manual, Page: 166 / 1376

Frequency Modulated Phase-Locked Loop (FMPLL)
PXN20 Microcontroller Reference Manual, Rev. 1
7-4 Freescale Semiconductor
LOC Loss-Of-Clock Status. The LOC bit is an indication of whether a loss-of-clock condition is present when operating
in normal PLL mode. If LOC = 0, the system clocks are operating normally. If LOC = 1, the system clocks have
failed due to a reference failure or a PLL failure. If the read of the LOC bit and the loss-of-clock condition occur
simultaneously, the bit does not reflect the current loss-of-clock condition. If a loss-of-clock condition occurs that
sets this bit and the clocks later return to normal, this bit is cleared. LOC is always zero in PLL Off mode.
0 Clocks are operating normally.
1 Clocks are not operating normally.
MODE Clock Mode. The state of this bit, along with PLLSEL and PLLREF, indicates which clock mode the PLL is
operating in (see
Table 7-3 ). The value of ESYNCR1[CLKCFG0] is reflected in this location.
0 PLL Off mode.
1 PLL clock mode.
PLLSEL PLL Mode Select. The state of this bit, along with MODE and PLLREF, indicates which mode the PLL operates
in (see
Table 7-3 ). This bit is cleared in PLL Off mode. The value of ESYNCR1[CLKCFG1] is reflected in this
location.
0 PLL Off mode.
1 Normal PLL mode.
PLLREF PLL Clock Reference Source. The state of this bit, along with MODE and PLLSEL, indicates which reference
source has been chosen for normal PLL mode (see
Table 7-3 ). This bit is cleared in PLL Off mode. The value of
ESYNCR1[CLKCFG2] is reflected in this location.
0 External clock reference chosen.
1 Crystal clock reference chosen.
Note: The user must also use the XOSC bit in the CRP_CLKSRC register to enable the 4 – 40 MHz oscillator.
LOCKS Sticky PLL Lock Status Bit. The LOCKS bit is a sticky indication of PLL lock status. LOCKS is set by the lock
detect circuitry when the PLL acquires lock after: 1) a system reset, or 2) a write to the ESYNCR2 which modifies
the ESYNCR2[EMFD] bits, or 3) frequency modulation is enabled. Whenever the PLL loses lock, LOCKS is
cleared. LOCKS remains cleared after the PLL re-locks, until one of the three conditions occurs. Furthermore, if
the LOCKS bit is read when the PLL simultaneously loses lock, the bit does not reflect the current loss-of-lock
condition.
If operating in PLL Off mode, LOCKS remains cleared after reset.
0 PLL has lost lock since last system reset, a write to ESYNCR1 to modify the ESYNCR1[EMFD] bit field, or
frequency modulation enabled
1 PLL has not lost lock since last system reset, a write to ESYNCR1 to modify the ESYNCR1[EMFD] bit field,
or frequency modulation enabled
LOCK PLL Lock Status Bit. The LOCK bit indicates whether the PLL has acquired lock. PLL lock occurs when the
synthesized frequency matches to within approximately 0.75% of the programmed frequency. The PLL loses lock
when a frequency deviation of greater than approximately 1.5% occurs. If the LOCK bit is read when the PLL
simultaneously loses lock or acquires lock, the bit does not reflect the current condition of the PLL.
If operating in PLL Off mode, LOCK remains cleared after reset.
0 PLL is unlocked
1 PLL is locked
LOCF Loss-of-Clock Flag. This bit provides the interrupt request flag. To clear the flag, write a 1 to the bit. Writing 0 has
no effect. Asserting reset clears the flag. If clocks return to normal after the flag has been set, the bit remains set
until cleared by either writing 1 or asserting reset. A loss-of-clock condition can only be detected if LOCEN = 1.
0 Interrupt service not requested.
1 Interrupt service requested.
Table 7-2. SYNSR Register Field Descriptions (continued)
Field Description