NXP Semiconductors PXN2020, Reference Manual, Page: 392 / 1376

e200z6 Core (Z6)
PXN20 Microcontroller Reference Manual, Rev. 1
13-28 Freescale Semiconductor
13.3.2.6 L1 Cache Configuration Register 0 (L1CFG0)
The L1 cache configuration register 0 (L1CFG0) is a 32-bit read-only register. L1CFG0 provides
information about the configuration of the Zen Z650n3e L1 cache design. The contents of the L1CFG0
register can be read using a
mfspr instruction. The SPR number for L1CFG0 is 515 in decimal. The
L1CFG0 register is shown in Figure 13-17 .
The L1CFG0 bits are described in Table 13-11 .
24–26 — Reserved
27 CORG
Cache organization
0 The cache is organized as 128 sets and 8 ways
1 The cache is organized as 256 sets and 4 ways.
Selecting CORG = 1 helps minimize power consumption.
28 — Reserved
29 CABT
Cache operation aborted. Indicates a cache invalidate or a cache lock bits flash clear operation
was aborted prior to completion. This bit is set by hardware on an aborted condition, and
remains set until cleared by software writing 0 to this bit location.
30 CINV
Cache invalidate
0 No cache invalidate
1 Cache invalidation operation
When written to a 1, a cache invalidation operation is initiated by hardware. After this is
complete, this bit is reset to 0. Writing a 1 while an invalidation operation is in progress results
in an undefined operation. Writing a 0 to this bit while an invalidation operation is in progress is
ignored. Cache invalidation operations require approximately cycles to complete. Invalidation
occurs regardless of the enable (CE) value.
31 CE
Cache Enable
0 Cache is disabled
1 Cache is enabled.
When disabled, cache lookups are not performed for normal load or store accesses.
Other L1CSR0 cache control operations are still available. Also, operation of the store buffer is
not affected by CE.
CARCH
CWP
A
CF
AH
A
CFISW
A
0
CBSIZE
CREPL
CLA CP
A
CNW
A
Y
CSIZE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
01 1 0 1 0 0 00 10 1 1
00000111 (8 way) /
00000011 (4 way)
00000100000 (32 KB)
SPR - 515; Read-only
Figure 13-17. L1 Cache Configuration Register 0 (L1CFG0)
Table 13-10. L1CSR0 Field Descriptions (continued)
Bits Name Description