NXP Semiconductors PXN2020, Reference Manual, Page: 405 / 1376

e200z0 Core (Z0)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 14-7
Figure 14-3. e200 User Mode Program Model
General purpose registers (GPRs) are accessed through instruction operands. Access to other registers can
be explicit (by using instructions for that purpose such as Move to Special Purpose Register (
mtspr
) and
Move from Special Purpose Register (
mfspr
) instructions) or implicit as part of the execution of an
instruction. Some registers are accessed both explicitly and implicitly.
14.3.1 Power Architecture Book E Registers
e200 supports a subset of the registers defined by Power Architecture™ Book E Specification . Notable
exceptions are the Floating Point registers FPR0-FPR31 and FPSCR. e200z0 does not support the Book E
floating-point architecture. The e200-supported Power Architecture Book E registers are described as
follows (e200-specific registers are described in the
Section 14.3.2, e200-Specific Special Purpose
Registers ):
14.3.1.1 User-Level Registers
The user-level registers can be accessed by all software with either user or supervisor privileges. They
include the following:
• General-purpose registers (GPRs). The thirty-two 32-bit GPRs (GPR0–GPR31) serve as data
source or destination registers for integer instructions and provide data for generating addresses.
• Condition register (CR). The 32-bit CR consists of eight 4-bit fields, CR0–CR7, that reflect results
of certain arithmetic operations and provide a mechanism for testing and branching. See Condition
Register (CR), in Chapter 3, Branch and Condition Register Operations, of
Power Architecture
Book E Specification .
The remaining user-level registers are SPRs. Note that the Power Architecture Book E provides the
mtspr
and
mfspr
instructions for accessing SPRs.
USER Mode Programmer Model
SPR 9
General-Purpose
Registers
Count Register
CTR
SPR 8
Link Register
LR
Condition Register
CR
GPR0
GPR1
GPR31
SPR 1
XER
XER
General Registers
Cache Registers
SPR 515
Cache Configuration
(Read-only)
L1CFG0