Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
25-15
25.3.4.7
MII Management Frame Register (MMFR)
The MMFR is accessed by the user and does not reset to a defined value. The MMFR register is used to
communicate with the attached MII compatible PHY devices, providing read/write access to their MII
registers. Performing a write to the MMFR causes a management frame to be sourced unless the MSCR
has been programmed to 0. In the case of writing to MMFR when MSCR = 0, if the MSCR register is then
written to a non-zero value, an MII frame is generated with the data previously written to the MMFR. This
allows MMFR and MSCR to be programmed in either order if MSCR is currently zero.
Table 25-8. ECR Field Descriptions
Bits
Description
ETHER_EN
When this bit is set, the FEC is enabled, and reception and transmission are possible. When this bit is
cleared, reception is immediately stopped and transmission is stopped after a bad CRC is appended to any
currently transmitted frame. The buffer descriptors for an aborted transmit frame are not updated after
clearing this bit. When ETHER_EN is deasserted, the DMA, buffer descriptor, and FIFO control logic are
reset, including the buffer descriptor and FIFO pointers. The ETHER_EN bit is altered by hardware under
the following conditions:
• ECR[RESET] is set by software, in which case ETHER_EN is cleared
• An error condition causes the EIR[EBERR] bit to set, in which case ETHER_EN is cleared
RESET
When this bit is set, the equivalent of a hardware reset is performed but it is local to the FEC. ETHER_EN
is cleared and all other FEC registers take their reset values. Also, any transmission/reception currently in
progress is abruptly aborted. This bit is automatically cleared by hardware during the reset sequence. The
reset sequence takes approximately 8 system clock cycles after RESET is written with a 1.
Offset: FE 0x0040
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
ST
OP
PA
RA
TA
W
Reset
U
1
1
“U” signifies a bit that is uninitialized.
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
DATA
W
Reset
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
Figure 25-7. MII Management Frame Register (MMFR)
Summary of Contents for PXN2020
Page 1: ...PXN20 Microcontroller Reference Manual Devices Supported PXN2020 PXN2120 PXN20RM Rev 1 06 2011...
Page 42: ...PXN20 Microcontroller Reference Manual Rev 1 lxiv Freescale Semiconductor...
Page 64: ...Introduction PXN20 Microcontroller Reference Manual Rev 1 1 22 Freescale Semiconductor...
Page 112: ...Signal Description PXN20 Microcontroller Reference Manual Rev 1 3 44 Freescale Semiconductor...
Page 118: ...Resets PXN20 Microcontroller Reference Manual Rev 1 4 6 Freescale Semiconductor...
Page 372: ...e200z6 Core Z6 PXN20 Microcontroller Reference Manual Rev 1 13 8 Freescale Semiconductor...
Page 412: ...e200z0 Core Z0 PXN20 Microcontroller Reference Manual Rev 1 14 14 Freescale Semiconductor...
Page 821: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 Freescale Semiconductor 27 49...
Page 822: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 27 50 Freescale Semiconductor...
Page 1376: ...Memory Map PXN20 Microcontroller Reference Manual Rev 1 A 118 Freescale Semiconductor...