NXP Semiconductors PXN2020, Reference Manual, Page: 1067 / 1376

Inter-Integrated Circuit Bus Controller Module (I
2
C)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 32-23
After the last DMA write (TX mode) to the I
2
C the module immediately starts the next I
2
C-bus transfer.
The same is true for RX mode. After the DMA read from the IBDR register the module initiates the next
I
2
C-bus transfer. This results in two possible scenarios in the DMA mode exiting scheme.
1. Fast reaction
The DMAEN bit is cleared before the next I
2
C-bus transfer completes. In this case, the module
raises an interrupt request to the CPU which can be serviced normally.
2. Slow reaction
The DMAEN bit is cleared after the next I
2
C-bus transfer has already completed. In this case, the
module does not raise an interrupt request to the CPU. Instead, the TCF bit can be read to determine
that the transfer completed and the module is ready for further transfer.
32.5.2.3.1 Fast vs. Slow Reaction
The reaction time T
R
for the system to disable DMAEN after the last DMA controller access to the I
2
C is
the time required for one byte transfer over the I
2
C. In a fast reaction the disabling has to occur before the
ninth bit of the data transfer, which is the ACK bit. So the time available is eight times the SCL period.
T
R
= 8 x T
SCL
Eqn. 32-5
In fast mode, with 400 kbit/s, T
SCL
is 2.5

s, so T
R
is 20

s.
Depending on the system and DMA controller there are different possibilities for the deassertion of
DMAEN. Three options are:
1. CPU intervention via interrupt
The DMA controller is programmed to signal an interrupt to the CPU which is then responsible for
the deassertion of DMAEN. This scheme is supported by most systems but can result in a slow
reaction time if higher priority interrupts interfere. Therefore, the interrupt handling routine can
become complicated as it has to check which of the two scenarios happened (check TCF bit) and
act accordingly. In case of slow reaction you can force an interrupt for the I
2
C in the interrupt
controller to have the further transfer handled by the normal I
2
C interrupt routine. The use of nested
interrupts can cause problems in this scenario, if the DMA interrupt stalls between the deassertion
and the DMAEN bit and the checking of the TCF bit.
2. DMA channel linking (if supported)
The transfer control descriptor in the DMA controller that performs the data transfer is linked to
another channel that does a write to the I
2
C IBCR register to disable the DMAEN bit. This is
probably the fastest system solution, but it uses two DMA channels. On the system level, no higher
priority DMA requests must occur between the two linked TCDs because those can result in slow
reaction.
3. DMA scatter/gather process (if supported)
The transfer control descriptor in the DMA controller that performs the data transfer has the
scatter-gather feature activated. This feature initiates a reload of another TCD from system RAM
after the completion of the first TCD. The new TCD has its start bit already set and immediately
starts the required write to the I
2
C IBCR register to disable the DMAEN bit. This TCD also has
scatter-gather activated and is programmed to reload the initial TCD upon completion, bringing the