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System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
8-58
Freescale Semiconductor
8.3.2.47
Masked Serial GPO Register for DSPI_A Low (SIU_DSPIAL)
The SIU_DSPIAL register allows any combination of bits in the bottom half of the 32-bit serialized data
frame from DSPI_A to be updated with a single 32-bit write operation, while allowing other bits to
maintain their previous state. This is accomplished by writing a 16-bit masked value coherently with an
update value contained in a 16-bit output field, and only updating those bits in the output register for which
the corresponding mask bit is set.
8.3.2.48
Masked Serial GPO Register for DSPI_B High (SIU_DSPIBH)
The SIU_DSPIBH register allows any combination of bits in the top half of the 32-bit serialized data frame
from DSPI_B to be updated with a single 32-bit write operation, while allowing other bits to maintain their
previous state. This is accomplished by writing a 16-bit masked value coherently with an update value
contained in a 16-bit output field, and only updating those bits in the output register for which the
corresponding mask bit is set.
Offset:
SI 0x0D04
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R MASK
15
MASK
14
MASK
13
MASK
12
MASK
11
MASK
10
MASK
9
MASK
8
MASK
7
MASK
6
MASK
5
MASK
4
MASK
3
MASK
2
MASK
1
MASK
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R DATA
15
DATA
14
DATA
13
DATA
12
DATA
11
DATA
10
DATA
9
DATA
8
DATA
7
DATA
6
DATA
5
DATA
4
DATA
3
DATA
2
DATA
1
DATA
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-55. Masked Serial GPO Register for DSPI_A Low (SIU_DSPIAL)
Table 8-34. SIU_DSPIAL Field Descriptions
Field
Description
MASKn
Mask Bit. This bit controls the write access to the corresponding GPO for DSPI_A.
0 The previous value defined by GPO for DSPI_A is maintained.
1 The corresponding GPO for DSPI_A is written with the value defined by the DATAn field.
DATAn
Pin Data Out. This bit stores the data to be driven out on the GPO for DSPI_A output controlled by this register.
0 Logic low value is driven for the corresponding GPO for DSPI_A when this output is selected in the DSPI
serialization module.
1 Logic high value is driven for the corresponding GPO for DSPI_A when this output is selected in the DSPI
serialization module.
Summary of Contents for PXN2020
Page 1: ...PXN20 Microcontroller Reference Manual Devices Supported PXN2020 PXN2120 PXN20RM Rev 1 06 2011...
Page 42: ...PXN20 Microcontroller Reference Manual Rev 1 lxiv Freescale Semiconductor...
Page 64: ...Introduction PXN20 Microcontroller Reference Manual Rev 1 1 22 Freescale Semiconductor...
Page 112: ...Signal Description PXN20 Microcontroller Reference Manual Rev 1 3 44 Freescale Semiconductor...
Page 118: ...Resets PXN20 Microcontroller Reference Manual Rev 1 4 6 Freescale Semiconductor...
Page 372: ...e200z6 Core Z6 PXN20 Microcontroller Reference Manual Rev 1 13 8 Freescale Semiconductor...
Page 412: ...e200z0 Core Z0 PXN20 Microcontroller Reference Manual Rev 1 14 14 Freescale Semiconductor...
Page 821: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 Freescale Semiconductor 27 49...
Page 822: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 27 50 Freescale Semiconductor...
Page 1376: ...Memory Map PXN20 Microcontroller Reference Manual Rev 1 A 118 Freescale Semiconductor...