NXP Semiconductors PXN2020, Reference Manual, Page: 501 / 1376

Periodic Interrupt Timer (PIT)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 22-7
22.3.2.5 Timer n Flag Register (TFLGn)
These registers hold the PIT interrupt flags.
Table 22-6. TCTRLn Field Descriptions
Field Description
TIE Timer Interrupt Enable Bit.
0 Interrupt requests from Timer n are disabled.
1 Interrupt will be requested whenever TIF is set.
When an interrupt is pending (TIF set), enabling the interrupt will immediately cause an interrupt event. To
avoid this, the associated TIF flag must be cleared first.
TEN Timer Enable Bit.
0 Timer is disabled.
1 Timer is active.
Offset: Channe 0x000C
LDVAL1 = 0x010C
LDVAL2 = 0x011C
LDVAL3 = 0x012C
LDVAL4 = 0x013C LDVAL5 = 0x014C
LDVAL6 = 0x015C
LDVAL7 = 0x016C
LDVAL8 = 0x017C
Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TIF
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Figure 22-6. Timer n Flag Register (TFLGn)
Table 22-7. TFLGn Field Descriptions
Field Description
TIF Time Interrupt Flag. TIF is set to 1 at the end of the timer period.This flag can be cleared only by writing it with
a 1. Writing a 0 has no effect. If enabled (TIE = 1), TIF causes an interrupt request.
0 Time-out has not yet occurred.
1 Time-out has occurred.