NXP Semiconductors PXN2020, Reference Manual, Page: 1227 / 1376

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 36-77
Development control register 2 is shown in Figure 36-54 and its fields are described in Table 36-50 .
NOTE
The EOC bits in DC1 must be programmed to trigger EVTO on watchpoint
occurrence for the EWC bits to have any effect.
OVC[2:0] Overrun control.
000 Generate overrun messages
001–010 Reserved
011 Delay processor for BTM / DTM / OTM overruns
1XX Reserved
EIC[1:0] EVTI control.
00 EVTI is used for synchronization (program trace/ data trace)
01 EVTI is used for debug request
1X Reserved
TM[2:0] Trace mode. Any or all of the TM bits may set, enabling one or more traces.
000 No trace
1XX Program trace enabled
X1X Data trace enabled
XX1 Ownership trace enabled
1
The output port mode control bit (OPC) and MCKO divide bits (MCK_DIV) are shown for clarity. These functions are controlled
globally by the NPC port control register (PCR). These bits are writable in the PCR but have no effect.
Nexus Reg: 0x3 Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
EWC
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 36-54. Development Control Register 2 (DC2)
Table 36-50. DC2 Field Descriptions
Field Description
EWC[7:0] EVTO watchpoint configuration. Any or all of the bits in EWC may be set to configure the EVTO watchpoint.
00000000No Watchpoints trigger EVTO
1XXXXXXXWatchpoint #0 (IAC1 from Nexus1) triggers EVTO
X1XXXXXXWatchpoint #1 (IAC2 from Nexus1) triggers EVTO
XX1XXXXXWatchpoint #2 (IAC3 from Nexus1) triggers EVTO
XXX1XXXXWatchpoint #3 (IAC4 from Nexus1) triggers EVTO
XXXX1XXXWatchpoint #4 (DAC1 from Nexus1) triggers EVTO
XXXXX1XXWatchpoint #5 (DAC2 from Nexus1) triggers EVTO
Table 36-49. DC1 Field Descriptions (continued)
Field Description