NXP Semiconductors PXN2020, Reference Manual, Page: 1228 / 1376

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
36-78 Freescale Semiconductor
36.7.7.2 Development Status Register (DS)
The development status register is used to report system debug status. When debug mode is entered or
exited, or an e200z0-defined low power mode is entered, a debug status message is transmitted with
DS[31:24]. The external tool can read this register at any time.
36.7.7.3 Read/Write Access Control/Status (RWCS)
The read write access control/status register provides control for read/write access. Read/write access
provides DMA-like access to memory-mapped resources on the system bus either while the processor is
halted, or during runtime. The RWCS register also provides read/write access status information as shown
in
Table 36-52 .
Nexus Reg: 0x4 Access: User read only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DBG 0 0 0 LPC CHK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 36-55. Development Status Register (DS)
Table 36-51. DS Field Descriptions
Field Description
DBG e200z0 CPU debug mode status.
0 CPU not in debug mode
1 CPU in debug mode (jd_debug_b signal asserted)
LPC[1:0] e200z0 CPU low power mode status.
00 Normal (run) mode
01 CPU in halted state
10 CPU in stopped state
11 Reserved
CHK e200z0 CPU checkstop status.
0 CPU not in checkstop state
1 CPU in checkstop state