
Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
31-13
31.3.2.7
eSCI LIN Control Register 1 (eSCI_LCR1)
This register provides control bits to control and configure the LIN hardware. This register provides the
interrupt enable bits for the interrupt flags in Interrupt Flag and Status Register 2 (eSCI_IFSR2).
Offset: ESC 0x000A
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
RX
RDY
TX
RDY
L
WAKE
STO
PB
ERR
CERR
CK
ERR
FRC
0
0
0
0
0
0
UREQ OVFL
W
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
Reset
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 31-7. eSCI Interrupt Flag and Status Register 2 (eSCI_IFSR2)
Table 31-8. LINSTAT1 Field Descriptions
Field
Description
RXRDY
Receive Data Ready Interrupt Flag. This interrupt flag is set when the payload data of a received frame is
transferred into the LIN Receive Register (eSCI_LRR).
TXRDY
Transmit Data Ready Interrupt Flag. This interrupt flag is set when the content of the LIN Transmit Register
(eSCI_LTR) is processed by the LIN PE either to generate a frame header or to transmit frame data.
LWAKE
LIN Wakeup Received Flag. This interrupt flag is set when a LIN wakeup character is received, as described in
STO
Slave Timeout Interrupt Flag. This interrupt flag is set when a Slave-Not-Responding-Error is detected. A
detailed description is given in
Section 31.4.6.5.5, Slave-Not-Responding-Error Detection.
PBERR
Physical Bus Error Flag. This interrupt flag is set when the receiver input remains unchanged for at least 31
RCLK clock cycles after the start of a byte transmission, as described in
Section 31.4.6.5, LIN Error Reporting.
CERR
CRC Error Flag. This interrupt flag is set when an incorrect CRC pattern was detected for a received LIN frame.
CKERR
Checksum Error Flag. This interrupt flag is set when a checksum error was detected for a received LIN frame.
FRC
Frame Complete Flag. This interrupt flag is set when a LIN frame was completely transmitted or received.
UREQ
Unrequested Data Received Flag. This interrupt flag is set when unrequested activity has been detected on the
LIN bus, as described in
Section 31.4.6.5, LIN Error Reporting.
OVFL
Overflow Flag. This interrupt flag is set when an overflow as described in
Section 31.4.6.5.8, Overflow Detection,
was detected.
Offset: ESC 0x000C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
LRES
WU
WUD
0
0
PRTY
LIN
RXIE
TXIE WUIE STIE
PBIE
CIE
CKIE
FCIE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 31-8. eSCI LIN Control Register 1 (eSCI_LCR1)
Summary of Contents for PXN2020
Page 1: ...PXN20 Microcontroller Reference Manual Devices Supported PXN2020 PXN2120 PXN20RM Rev 1 06 2011...
Page 42: ...PXN20 Microcontroller Reference Manual Rev 1 lxiv Freescale Semiconductor...
Page 64: ...Introduction PXN20 Microcontroller Reference Manual Rev 1 1 22 Freescale Semiconductor...
Page 112: ...Signal Description PXN20 Microcontroller Reference Manual Rev 1 3 44 Freescale Semiconductor...
Page 118: ...Resets PXN20 Microcontroller Reference Manual Rev 1 4 6 Freescale Semiconductor...
Page 372: ...e200z6 Core Z6 PXN20 Microcontroller Reference Manual Rev 1 13 8 Freescale Semiconductor...
Page 412: ...e200z0 Core Z0 PXN20 Microcontroller Reference Manual Rev 1 14 14 Freescale Semiconductor...
Page 821: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 Freescale Semiconductor 27 49...
Page 822: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 27 50 Freescale Semiconductor...
Page 1376: ...Memory Map PXN20 Microcontroller Reference Manual Rev 1 A 118 Freescale Semiconductor...