NXP Semiconductors PXN2020, Reference Manual, Page: 377 / 1376

e200z6 Core (Z6)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 13-13
13.2.2.2 Supervisor-Level Registers
The following supervisor-level registers are defined in the e200z6 core in addition to the Power
Architecture embedded category registers described previously:
• Configuration registers
— Hardware implementation-dependent 0 (HID0) controls processor and system functions.
— Hardware implementation-dependent 1 (HID1) controls processor and system functions.
• Exception handling and control registers
— Debug save and restore registers (DSRR0, DSRR1). DSRR0 holds the effective address for the
instruction at which execution resumes when an rfdi instruction is executed at the end of a
debug interrupt handler routine. DSRR1 is used to save machine state on a debug interrupt, and
stores the MSR register contents. The MSR value is restored when an
rfdi instruction is
executed at the end of a debug interrupt handler routine.
— When enabled, the DSRR0 register is used to save the address of the instruction at which
execution continues when rfdi executes at the end of a debug interrupt handler routine.
— Interrupt vector offset registers (IVOR32–IVOR34). These registers provide the address of the
interrupt handler for different classes of interrupts.
• Debug facility registers
— Debug control register 3 (DBCR3) controls for debug functions not described in the
Power Architecture embedded category.
— Debug counter register (DBCNT) provides counter capability for debug functions.
• Cache registers
— L1 cache configuration register (L1CFG0) is a read-only register that allows software to query
the configuration of the L1 cache.
— L1 cache control and status register (L1CSR0) controls the operation of the L1 unified cache
such as cache enabling, cache invalidation, cache locking, or 8 etc.
— L1 cache flush and invalidate register (L1FINV0) controls software flushing and invalidation
of the L1 unified cache.
• Memory management unit registers
— MMU configuration register (MMUCFG) is a read-only register that allows software to query
the configuration of the MMU.
— MMU assist (MAS0–MAS4, MAS6) registers provide the interface to the core from the
memory management unit.
— MMU control and status register (MMUCSR0) controls invalidation of the MMU.
— TLB configuration registers (TLBCFG0, TLBCFG1) are read-only registers that allow
software to query the configuration of the TLBs.
• System version register (SVR) is a read-only and identifies the version (model) and revision level
of the system with an e200z6 processor built on the Power Architecture embedded category.
For more details about these registers, refer to the e200z6 core reference documentation.