NXP Semiconductors PXN2020, Reference Manual, Page: 905 / 1376

Controller Area Network (FlexCAN)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 29-21
29.3.4.6 Error and Status Register (CANx_ESR)
This register reflects various error conditions, some general status of the device, and it is the source of four
interrupts to the CPU. The reported error conditions (bits 16–21) are those that occurred since the last time
the CPU read this register. The CPU read action clears bits 16–23. Bits 22–28 are status bits.
Most bits in this register are read-only, except TWRN_INT, RWRN_INT, BOFF_INT, and ERR_INT,
which are interrupt flags that can be cleared by writing 1 to them (writing 0 has no effect).
NOTE
A read clears BIT1
_
ERR, BIT0
_
ERR, ACK
_
ERR, CRC
_
ERR, FRM
_
ERR,
and STF
_
ERR, therefore these bits must not be read speculatively.
Offset: Base + 0x001C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
RXECTR TXECTR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 29-9. Error Counter Register (CANx_ECR)
Offset: Base + 0x0020 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0
TWRN_
INT
RWRN_
INT
W w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R BIT1_
ERR
BIT0_
ERR
ACK_
ERR
CRC_
ERR
FRM_
ERR
STF_
ERR
TX_
WRN
RX_
WRN
IDL
E
TXR
X
FLT_CONF 0
BOFF_
INT
ERR_
INT
0
W r1c r1c r1c r1c r1c r1c r1c r1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 29-10. Error and Status Register (CANx_ESR)