NXP Semiconductors PXN2020, Reference Manual, Page: 979 / 1376

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 30-53
Figure 30-37. Continuous SCK Timing Diagram (CONT = 1)
30.4.10 Timed Serial Bus (TSB)
The DSPI can be programmed in timed serial bus (TSB) configuration by asserting the TSBC bit in the
DSPI_DSICR register. See
Section 30.3.2.10, DSPI DSI Configuration Register (DSPI_DSICR), for
details. To operate in TSB configuration, the DSPI must be in master mode and configured as DSI
(DCONF = 0b01). The TSB allows operating in continuous and non-continuous serial communication
clock (controlled by bit CONT_SCKE).
Figure 30-38 shows the signals used in the TSB interface. The SDR and ASDR registers are set to 32 bits
in this configuration, to allow the Micro Second Channel (MSC) feature to be performed.
In the TSB configuration, the DSPI can send from 4 to as many as 32 data bits. The source of these bits
can be either the DSPI DSI Alternate Serialization Data Register (DSPI_ASDR), written by the host
software, or the parallel input pin states latched into the DSPI DSI Serialization Data Register
(DSPI_SDR).
Figure 30-38. DSPI Usage in the TSB Configuration
The same constraints that apply to DSI are valid for TSB except for the frame size and the Delay After
Transfer value (T
DT
). The TSB configuration allows from 4 to 32 bits frame size to be used, and T
DT
can
be programmable to a minimum of 1 × T
SCK
, allowing a programmable inter-message gap. See
Table 30-10 and Table 30-30 for details on programming the T
DT
values.
SCK
(CPOL = 0)
PCS
SCK
(CPOL = 1)
Master SOUT
Master SIN
Transfer 1 Transfer 2
SOUT (Downstream Frame)
SCK
PCS
DSI
(Master)
32 Bit Data
Register
(ASDR)
32 Bit
(SDR)
Serial Data
GPIO or COMMAND
Data Writes
Parallel
Inputs