NXP Semiconductors PXN2020, Reference Manual, Page: 384 / 1376

e200z6 Core (Z6)
PXN20 Microcontroller Reference Manual, Rev. 1
13-20 Freescale Semiconductor
13.3.1.5.4 MAS[3] Register
The MAS[3] register is shown in Figure 13-10 .
MAS[3] fields are defined in Table 13-7 .
13.3.1.5.5 MAS[4] Register
The MAS[4] register is shown in Figure 13-11 .
MAS[4] fields are defined in Table 13-8 .
G Guarded. The e200z6 ignores the guarded attribute because no speculative or out-of-order processing is performed.
0 Access to this page are not guarded, and can be performed before it is known if they are required by the sequential
execution model.
1 All loads and stores to this page are performed without speculation (that is, they are known to be required).
E Endianness. Determines endianness for the corresponding page.
0 The page is accessed in big-endian byte order.
1 The page is accessed in true little-endian byte order.
SPR: 627 Access: Read/write
Permission Bits
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
RPN — U0 U1 U2 U3 UX SX UW SW UR SR
W
Reset Undefined on Power Up

Unchanged on Reset
Figure 13-10. MMU Assist Register 3—MAS[3]
Table 13-7. MAS[3]—RPN and Access Control
Field Description
RPN Real page number. Only bits that correspond to a page number are valid. Bits that represent offsets within a page
are ignored and must be zero.
U0–U3 User bits.
PERMIS Permission bits (UX, SX, UW, SW, UR, SR).
SPR: 628 Access: Read/write
Default WIMGE values
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
— TLBSELD — TIDSELD — TSIZED —
VL
ED
WD ID MD GD ED
W
Reset Undefined on Power Up

Unchanged on Reset
Figure 13-11. MMU Assist Register 4 MAS[4]
Table 13-6. MAS[2]—EPN and Page Attributes (continued)
Field Description