NXP Semiconductors PXN2020, Reference Manual, Page: 971 / 1376

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 30-45
The DSPI supports four different transfer formats:
• Classic SPI with CPHA = 0
• Classic SPI with CPHA = 1
• Modified transfer format with CPHA = 0
• Modified transfer format with CPHA = 1
A modified transfer format is supported to allow for high-speed communication with peripherals that
require longer setup times. The DSPI can sample the incoming data later than halfway through the cycle
to give the peripheral more setup time. The MTFE bit in the DSPI_MCR selects between Classic SPI
Format and Modified Transfer Format. The Classic SPI Formats are described in
Section 30.4.8.1, Classic
SPI Transfer Format (CPHA = 0), and Section 30.4.8.2, Classic SPI Transfer Format (CPHA = 1). The
Modified Transfer Formats are described in Section 30.4.8.3, Modified SPI/DSI Transfer Format
(MTFE = 1, CPHA = 0), and Section 30.4.8.4, Modified SPI/DSI Transfer Format (MTFE = 1,
CPHA = 1).
In the SPI and DSI configurations, the DSPI provides the option of keeping the PCS signals asserted
between frames. See
Section 30.4.8.5, Continuous Selection Format, for details.
30.4.8.1 Classic SPI Transfer Format (CPHA = 0)
The transfer format shown in Figure 30-29 is used to communicate with peripheral SPI slave devices
where the first data bit is available on the first clock edge. In this format, the master and slave sample their
SIN pins on the odd-numbered SCK edges and change the data on their SOUT pins on the even-numbered
SCK edges.