NXP Semiconductors PXN2020, Reference Manual, Page: 975 / 1376

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 30-49
last bit on the last edge of the SCK. The master samples the last slave SOUT bit one half SCK cycle after
the last edge of SCK. No clock edge is visible on the master SCK pin during the sampling of the last bit.
The SCK to PCS delay must be greater or equal to half of the SCK period.
NOTE
For correct operation of the modified transfer format, the user must
thoroughly analyze the SPI link timing budget.
Figure 30-32. DSPI Modified Transfer Format (MTFE = 1, CPHA = 1, Fsck = Fsys/4)
NOTE
When the DSPI is being used in the Modified Transfer Format mode
(DSPI_MCR[MTFE]=1) with the clock phase set for data changing on the
leading edge of the clock and captured on the following edge in the DSPI
Clock and Transfer Attributes Register (DSPI_CTARn[CPHA]=1), if the
After SCK delay scaler (ASC) time is set to less than 1/2 SCK clock period
the DSPI may not complete the transaction - the TCF flag will not be set,
serial data will not received, and last transmitted bit can be truncated.
In this case, the Modified Transfer Format mode is required
DSPI_MCR[MTFE]=1 with the clock phase set for serial data changing on
the leading edge of the clock and captured on the following edge in the SCK
clock (Transfer Attributes Register (DSPI_CTARn[CPHA]=1) make sure
that the ASC time is set to be longer than half SCK clock period.
30.4.8.5 Continuous Selection Format
Some peripherals must be deselected between every transfer. Other peripherals must remain selected
between several sequential serial transfers. The continuous selection format provides the flexibility to
handle both cases. The continuous selection format is enabled for the SPI configuration by setting the
t
CSC
= PCS to SCK delay.
t
ASC
= After SCK delay.
System clock
1 2 3 4 5 6
PCS
t
ASC
SCK
Master Sample
Master SOUT
Slave SOUT
Slave Sample
t
CSC