NXP Semiconductors PXN2020, Reference Manual, Page: 1050 / 1376

Inter-Integrated Circuit Bus Controller Module (I
2
C)
PXN20 Microcontroller Reference Manual, Rev. 1
32-6 Freescale Semiconductor
Figure 32-5. SCL Divider and SDA Hold
Table 32-3. IBFD Field Descriptions
Field Description
MULT I
2
C Multiplier Factor. The MULT bits define the multiplier factor mul. This factor is used along with the SCL divider to
generate the I
2
C baud rate. The multiplier factor mul as defined by the MULT bits is provided below.
00 mul = 1
01 mul = 2
10 mul = 4
11 Reserved
ICR I
2
C Bus Clock Rate. The ICR bits are used to prescale the bus clock for bit rate selection. These bits and the MULT
bits are used to determine the I
2
C baud rate, the SDA hold time, the SCL Start hold time and the SCL Stop hold time.
Table 32-4 provides the SCL divider and hold values for corresponding values of the ICR.
The SCL divider multiplied by multiplier factor mul is used to generate I
2
C baud rate.
I
2
C baud rate = bus speed (Hz)/(mul * SCL divider) Eqn. 32-1
SDA hold time is the delay from the falling edge of SDA (I
2
C data) to the changing of SDA (I
2
C data).
SDA hold time = bus period (s) * mul * SDA hold value Eqn. 32-2
SCL Start hold time is the delay from the falling edge of SDA (I
2
C data) while SCL is high (Start condition) to the
falling edge of SCL (I
2
C clock).
SCL Start hold time = bus period (s) * mul * SCL Start hold value Eqn. 32-3
SCL Stop hold time is the delay from the rising edge of SCL (I
2
C clock) to the rising edge of SDA
SDA (I
2
C data) while SCL is high (Stop condition).
SCL Stop hold time = bus period (s) * mul * SCL Stop hold value Eqn. 32-4
SDA
SCL
START condition STOP condition
SCL Hold(start)
SCL Hold(stop)