NXP Semiconductors PXN2020, Reference Manual, Page: 250 / 1376

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
8-68 Freescale Semiconductor
8.4 Functional Description
The following sections provide an overview of the SIU operation.
8.4.1 System Configuration
8.4.1.1 Boot Configuration
During the assertion of RESET, the BOOTCFG pin is used to load a value into the SIU_RSR[BOOTCFG]
bit, so the BAM program can determine the location of the reset configuration half word (RCHW), the boot
mode to be initiated, and whether to initiate a CAN or SCI boot. See
Section 9.3.3.1.1, Reset Configuration
Halfword Read, of the BAM chapter for detail on the RCHW. Table 8-49 defines the boot modes specified
by the SIU_RST[BOOTCFG] field.
8.4.1.2 Pad Configuration
The pad configuration registers (SIU_PCR) in the SIU allow software control of the static electrical
characteristics of external pins. The SIU_PCRs can select the multiplexed function of a pin, selection of
pullup or pulldown devices, the slew rate of I/O signals, open drain mode for output pins, and hysteresis.
8.4.2 Reset Control
The reset controller logic is located in the SIU. See Section 4.4, Reset Configuration, for reset operation
details.
8.4.3 External Interrupt
There are 16 external interrupt inputs, IRQ0–IRQ15, to the SIU. The IRQ n inputs can be configured for
rising- or falling-edge events or both. Each IRQ n input has a corresponding flag bit in the external interrupt
status register (SIU_EISR). The flag bits for the IRQ4–IRQ15 inputs are ORed together to form one
interrupt request to the interrupt controller. The flag bits for the IRQ1–IRQ0 inputs can generate an
interrupt request to the interrupt controller or a DMA transfer request to the DMA controller.
Figure 8-70
shows the DMA and interrupt request connections to the interrupt and DMA controllers.
Any pin used as an external interrupt must be configured in its SIU_PCR as a GPIO in input mode. In
addition, either rising and/or falling edge must be enabled in the SIU_IREER, or SIU_IFEER.
Two external inputs from pins PC6 and PC5 connect through the SIU to the critical interrupt input to the
Z0 and Z6 cores, respectively. These signals should be used as non-maskable interrupt (NMI) inputs.
The SIU contains an overrun interrupt enable for each IRQ and one combined overrun interrupt request to
the interrupt controller which is the logical OR of the individual overrun requests’ flags. Only the
Table 8-49. SIU_RSR[BOOTCFG] Configuration
Value Meaning
0b0 Boot from internal flash memory
0b1 CAN/SCI boot