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Memory Protection Unit (MPU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
18-15
18.4
Functional Description
In this section, the functional operation of the MPU is detailed. In particular, subsequent sections discuss
the operation of the access evaluation macro as well as the handling of error-terminated AHB bus cycles.
18.4.1
Access Evaluation Macro
As discussed, the basic operation of the MPU is performed in the access evaluation macro, a hardware
structure replicated in the two-dimensional connection matrix. As shown in
evaluation macro inputs the AHB system bus address phase signals (AHB_ap) and the contents of a region
descriptor (RGD
n
) and performs two major functions: region hit determination (
hit_b
) and detection of
an access protection violation (
error
).
Figure 18-11. MPU Access Evaluation Macro
is not a schematic of the actual access evaluation macro, but a generalized block diagram
showing the major functions included in this logic block.
M0SM
Bus Master 0 Supervisor Mode Access Control. This 2-bit field defines the access controls for bus master ID 0
(e200z6) when operating in supervisor mode. The M0SM field is defined as:
00
r, w, x =
read, write and execute allowed.
01
r, –, x =
read and execute allowed, but no write.
10
r, w, – =
read and write allowed, but no execute.
11 Same access controls as that defined by M0UM for user mode.
M0UM
Bus Master 0 User Mode Access Control. This 3-bit field defines the access controls for bus master ID 0 (e200z6)
when operating in user mode. The M0UM field consists of three independent bits, enabling read, write, and execute
permissions:
{r,w,x}
. If set, the bit allows the given access type to occur; if cleared, an attempted access of that
mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed.
Table 18-10. MPU_RGDAACn Field Descriptions (continued)
Field
Description
hit_b
start
end
error
>
>
RGDn
AHB_ap
hit & error
hit_b | error
>=
<=
r,w,x
Summary of Contents for PXN2020
Page 1: ...PXN20 Microcontroller Reference Manual Devices Supported PXN2020 PXN2120 PXN20RM Rev 1 06 2011...
Page 42: ...PXN20 Microcontroller Reference Manual Rev 1 lxiv Freescale Semiconductor...
Page 64: ...Introduction PXN20 Microcontroller Reference Manual Rev 1 1 22 Freescale Semiconductor...
Page 112: ...Signal Description PXN20 Microcontroller Reference Manual Rev 1 3 44 Freescale Semiconductor...
Page 118: ...Resets PXN20 Microcontroller Reference Manual Rev 1 4 6 Freescale Semiconductor...
Page 372: ...e200z6 Core Z6 PXN20 Microcontroller Reference Manual Rev 1 13 8 Freescale Semiconductor...
Page 412: ...e200z0 Core Z0 PXN20 Microcontroller Reference Manual Rev 1 14 14 Freescale Semiconductor...
Page 821: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 Freescale Semiconductor 27 49...
Page 822: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 27 50 Freescale Semiconductor...
Page 1376: ...Memory Map PXN20 Microcontroller Reference Manual Rev 1 A 118 Freescale Semiconductor...