NXP Semiconductors PXN2020, Reference Manual, Page: 53 / 1376

Introduction
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 1-11
• Supports operation of ADC using internal 16 MHz RC oscillator
• All unused analog pins available as general purpose input pins
• Selected unused analog pins available as general purpose output pins
• Power-down mode
• Supports for DMA transfer of results
1.7.8 Cross Triggering Unit (CTU)
The CTU features the following:
• Collection of 9 bit timers with an exponential prescaler able to generate the trigger event for ADC
conversions
• 9-bit down counters counting from a programmable start value to 0
• Different counters associated with different channel groups
• Channel group is defined based on PWM channel clock
• Different delay value for each eMIOS flag/PIT event
• 4-bit programmable exponential prescaler
• Single cycle delayed trigger output. Trigger output is a combination of 64 input flags/events
connected to different timers in the system
• Maskable interrupt generation whenever a trigger output is generated
• Event configuration registers dedicated to UC flag/triggering event
• Acknowledgement signal to eMIOS for clearing the flag
• Synchronization with ADC to avoid collision
NOTE
The CTU is available on the PXN21 only.
1.7.9 Serial Communication Interface Module (UART)
The PXN20 devices include up to two UART modules and support UART Master mode, UART Slave
mode and UART mode. The modules are UART state machine compliant to the UART 1.3 and 2.0 and 2.1
Specifications and handle UART frame transmission and reception without CPU intervention.
The serial communication interface module offers the following:
• UART features:
— Full-duplex operation
— Standard non return-to-zero (NRZ) mark/space format
— Data buffers with 4-byte receive, 4-byte transmit
— Configurable word length (8-bit or 9-bit words)
— Error detection and flagging
– Parity, noise and framing errors
— Interrupt driven operation with 4 interrupts sources