NXP Semiconductors PXN2020, Reference Manual, Page: 943 / 1376

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 30-17
Table 30-12. DSPI_SR Field Descriptions
Field Description
TCF Transfer Complete Flag. The TCF bit indicates that all bits in a frame have been shifted out. The TCF bit is set
at the end of the frame transfer. The TCF bit remains set until cleared by software.
0 Transfer not complete.
1 Transfer complete.
TXRXS TX & RX Status. The TXRXS bit reflects the status of the DSPI. See Section 30.4.2, Start and Stop of DSPI
Transfers, for information on how what causes this bit to be negated or asserted.
0 TX and RX operations are disabled (DSPI is in STOPPED state).
1 TX and RX operations are enabled (DSPI is in RUNNING state).
EOQF End of Queue Flag. The EOQF bit indicates that transmission in progress is the last entry in a queue. The
EOQF bit is set when TX FIFO entry has the EOQ bit set in the command halfword and the end of the transfer
is reached. The EOQF bit remains set until cleared by software. When the EOQF bit is set, the TXRXS bit is
automatically cleared.
0 EOQ is not set in the executing command.
1 EOQ bit is set in the executing SPI command.
TFUF Transmit FIFO Underflow Flag. The TFUF bit indicates that an underflow condition in the TX FIFO has occurred.
The transmit underflow condition is detected only for DSPI blocks operating in slave mode and SPI
configuration. The TFUF bit is set when the TX FIFO of a DSPI operating in SPI slave mode is empty, and a
transfer is initiated by an external SPI master. The TFUF bit remains set until cleared by software.
0 TX FIFO underflow has not occurred.
1 TX FIFO underflow has occurred.
TFFF Transmit FIFO Fill Flag. The TFFF bit provides a method for the DSPI to request more entries to be added to
the TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be cleared by host software
or an acknowledgement from the DMA controller when the TX FIFO is full.
0 TX FIFO is full.
1 TX FIFO is not full.
RFOF Receive FIFO Overflow Flag. The RFOF bit indicates that an overflow condition in the RX FIFO has occurred.
The bit is set when the RX FIFO and shift register are full and a transfer is initiated. The bit remains set until
cleared by software.
0 RX FIFO overflow has not occurred.
1 RX FIFO overflow has occurred.
RFDF Receive FIFO Drain Flag. The RFDF bit provides a method for the DSPI to request that entries be removed
from the RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be cleared by host software
or an acknowledgement from the DMA controller when the RX FIFO is empty.
0 RX FIFO is empty.
1 RX FIFO is not empty.
TXCTR TX FIFO Counter. The TXCTR field indicates the number of valid entries in the TX FIFO. The TXCTR is
incremented every time the DSPI _PUSHR is written. The TXCTR is decremented every time a SPI command
is executed and the SPI data is transferred to the shift register.
TXNXTPTR Transmit Next Pointer. The TXNXTPTR field indicates which TX FIFO Entry is transmitted during the next
transfer. The TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to the shift
register. See
Section 30.4.3.4, Transmit First-In First-Out (TX FIFO) Buffering Mechanism, for more details.
RXCTR RX FIFO Counter. The RXCTR field indicates the number of entries in the RX FIFO. The RXCTR is
decremented every time the DSPI _POPR is read. The RXCTR is incremented every time data is transferred
from the shift register to the RX FIFO.
POPNXTPTR Pop Next Pointer. The POPNXTPTR field contains a pointer to the RX FIFO entry that is returned when the
DSPI_POPR is read. The POPNXTPTR is updated when the DSPI_POPR is read. See Section 30.4.3.5,
Receive First-In First-Out (RX FIFO) Buffering Mechanism, for more details.