NXP Semiconductors PXN2020, Reference Manual, Page: 1072 / 1376

Cross Triggering Unit (CTU)
PXN20 Microcontroller Reference Manual, Rev. 1
33-4 Freescale Semiconductor
33.4.1.1 Control Status Register (CTU_CSR)
0x0094 CTU_EVTCFGR25
2
– Event Configuration Register 25 R/W
1
0x0000_0000 33.4.1.4/33-6 32
0x0098 CTU_EVTCFGR26
2
– Event Configuration Register 26 R/W
1
0x0000_0000 33.4.1.4/33-6 32
0x009C CTU_EVTCFGR27
2
– Event Configuration Register 27 R/W
1
0x0000_0000 33.4.1.4/33-6 32
0x00A0 CTU_EVTCFGR28
2
– Event Configuration Register 28 R/W
1
0x0000_0000 33.4.1.4/33-6 32
0x00A4 CTU_EVTCFGR29
2
– Event Configuration Register 29 R/W
1
0x0000_0000 33.4.1.4/33-6 32
0x00A8 CTU_EVTSELR30
2
– Event Configuration Register 30 R/W
1
0x0000_0000 33.4.1.4/33-6 32
0x00AC CTU_EVTSELR31
2
– Event Configuration Register 31 R/W
1
0x0000_0000 33.4.1.4/33-6 32
0x00B0 CTU_EVTSELR32
3
– Event Configuration Register 32 R/W
1
0x0000_0000 33.4.1.4/33-6 32
0x00B4–0x3FFF Reserved
1
Some bits are read-only.
2
For eMIOS channels 0 – 31.
3
For PIT3.
Offset: CT 0x0000 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0
TRGI
EN
TRGI 0 0
PRESC_CONF
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 33-2. Control Status Register (CTU_CSR)
Table 33-2. CTU_CSR Register Field Descriptions
Bit Description
TRGIEN Trigger Interrupt Request Enable
0 Trigger interrupt request disabled.
1 Trigger interrupt request enabled. A request is generated if the TRGI flag is set.
TRGI Trigger Interrupt Flag. This flag is set by hardware when the trigger output request is generated after a valid input
event is detected. It is cleared by software.
0 No trigger output request.
1 Trigger output request generated.
Table 33-1. CTU Memory Map
Offset from
CTU_BASE
0xFFFD_8000
Register Access Reset Value Section/Page Size