NXP Semiconductors PXN2020, Reference Manual, Page: 955 / 1376

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 30-29
shift register of the Slave, and vice versa. At the end of a transfer, the TCF bit in the DSPI_SR is set to
indicate a completed transfer.
Figure 30-18 illustrates how master and slave data is exchanged.
Figure 30-18. SPI and DSI Serial Protocol Overview
The DSPI has six peripheral chip select (PCS) signals that are used to select the slaves with which the DSPI
communicates.
The three DSPI configurations share transfer protocol and timing properties so they are described
independently of the configuration in
Section 30.4.8, Transfer Formats. The transfer rate and delay settings
are described in Section 30.4.7, DSPI Baud Rate and Clock Delay Generation.
See Section 30.4.13, Power Saving Features, for information on the power-saving features of the DSPI.
30.4.1 Modes of Operation
The DSPI modules have the following modes available:
• Master mode
• Slave mode
• Module disable mode
• Halt mode
• Debug mode
Master, slave, and module disable modes are module-specific modes. External halt and debug mode are
device-specific modes.
The module-specific modes are determined by bits in the DSPI_MCR. External halt and debug mode are
modes that the entire MCU can enter in parallel with the DSPI being configured in one of its block-specific
modes.
30.4.1.1 Master Mode
In master mode, the DSPI can initiate communications with peripheral devices. The DSPI operates as bus
master when the MSTR bit in the DSPI_MCR is set. The serial communications clock (SCK) is controlled
by the master DSPI. All three DSPI configurations are valid in master mode.
Shift Register
Baud Rate
Generator
Shift Register
SIN
SIN
SOUT
SOUT
SCK
SCK
SS
PCSx
DSPI Master DSPI Slave