NXP Semiconductors PXN2020, Reference Manual, Page: 793 / 1376

Media Local Bus (MLB)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 27-21
RDY Next Buffer Ready. System software should set this bit when all the registers, data, and program memory variables
are setup and ready to transmit or receive data using DMA. For TX data, the system memory buffer should also be
filled. For DMA using ping-pong buffering, hardware clears this bit after the buffer begins to be processed. For DMA
using circular buffering, software should clear this bit only when buffer processing needs to halted. If RDY is set
before processing of the Current Buffer is complete, status for the Current Buffer is reported using CSCRn[11:8]
(status bits for the previous buffer) and CSCRn[3:0] is not updated. The CSCRn[3:0] bits are only updated when the
processing for the Current Buffer is complete and the RDY bit has not yet been set.
0 Next buffer is not ready in system memory.
1 Next buffer is ready in system memory.
PBS Previous Buffer Start. When set, this bit indicates the first quadlet of the Previous Buffer has been successfully
transmitted or received. The setting of this bit generates a maskable channel interrupt to system software. This bit
is valid for all channel types.
0 First quadlet of the Previous Buffer has not been successfully transmitted or received.
1 First quadlet of the Previous Buffer has been successfully transmitted or received.
PBD Previous Buffer Done. When set, this bit indicates the last quadlet of the Previous Buffer has been successfully
transmitted or received. The setting of this bit generates a maskable channel interrupt to system software. This bit
is valid for all channel types. The Done status is always generated when the processing of a buffer has finished, even
if a Break or Error condition was detected during the packet processing. If Break or Error occurred, the Done status
bit is set in addition to the Break or Error status bit.
0 Last quadlet of the Previous Buffer has not been successfully transmitted or received.
1 Last quadlet of the Previous Buffer has been successfully transmitted or received.
PBDB Previous Buffer Detect Break. When set, this bit indicates that either a TX channel has detected a receiver break
response, ReceiverBreak (70h), or an RX channel has detected a transmitter break command, ControlBreak (36h)
or AsyncBreak (26h), while processing the Previous Buffer. The setting of this bit generates a maskable channel
interrupt to system software. This bit is valid for all channel types.
0 Break response was not detected while processing the Previous Buffer.
1 Break response was detected while processing the Previous Buffer.
PBPE Previous Buffer Protocol Error. When set, this bit indicates that either a TX channel has detected an RxStatus of
ReceiverProtocolError (72h), a RX channel has detected an invalid command for this channel type, or an additional
AsyncStart (20h) or ControlStart (30h) command has been received while in the middle of a packet. The setting of
this bit generates a maskable channel interrupt to system software. This bit is valid for all RX channels and valid for
only asynchronous and control TX channels.
0 Protocol error was not detected while processing the Previous Buffer.
1 Protocol error was detected while processing the Previous Buffer.
LFS Lost Frame Synchronization. When set, this bit indicates that the logical channel has lost synchronization with the
MediaLB frame. The setting of this bit generates a maskable channel interrupt to system software. This bit is valid
for synchronous channels only.
0 Frame synchronization not lost.
1 Frame synchronization lost.
HBE Host Bus Error. When set, this bit indicates that an error occurred on the host bus. If the channel is configured for
TX, then the bus error occurred during a read access. If the channel is configured for RX, then the bus error occurred
during a write access. The setting of this bit generates a non-maskable channel interrupt to system software. This
bit is valid for all channel types.
0 Bus error not detected.
1 Bus error detected.
Table 27-19. Channel n Status Configuration Register Field Descriptions (continued)
Field Description