NXP Semiconductors PXN2020, Reference Manual, Page: 1077 / 1376

Cross Triggering Unit (CTU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 33-9
Whenever a flag is set in a particular counter group, the corresponding counter loads the value from one
of the start value registers depending on the delay selection bits. An acknowledgement signal is sent to
eMIOS/PIT to clear the flag. In case more than one flag is set in the same counter group, the lower index
flag is given
priority and the corresponding delay value is loaded into the counter.
The acknowledgment signal can be forced to ‘1’ by setting the CLR_FLAG bit of the CTU_EVTCFGR n
register. These bits are implemented for only those input flags to which PIT flags are connected. The
purpose to provide these bits is to have the option of clearing PIT flags by software.
In summary, two levels of arbitration are done before the channel number and trigger are provided to the
ADC:
9 eMIOS Channel_9
10 eMIOS Channel_10
11 eMIOS Channel_11
12 eMIOS Channel_12
13 eMIOS Channel_13
14 eMIOS Channel_14
15 eMIOS Channel_15
16 eMIOS Channel_16
17 eMIOS Channel_17
18 eMIOS Channel_18
19 eMIOS Channel_19
20 eMIOS Channel_20
21 eMIOS Channel_21
22 eMIOS Channel_22
23 eMIOS Channel_23
24 eMIOS Channel_24
25 eMIOS Channel_25
26 eMIOS Channel_26
27 eMIOS Channel_27
28 eMIOS Channel_28
29 eMIOS Channel_29
30 eMIOS Channel_30
31 eMIOS Channel_31
32 PIT PIT_4
Table 33-9. CTU Trigger Sources (continued)
Trigger Number Module Source