NXP Semiconductors PXN2020, Reference Manual, Page: 350 / 1376

Flash Memory Array and Control
PXN20 Microcontroller Reference Manual, Rev. 1
12-24 Freescale Semiconductor
Offset: FLASH_REG 0x003C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
UTE SCBE
0 0 0 0 0 0
DSI
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0
MRE MRV EIE AIS AIE
AID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Figure 12-14. User Test Register 0 (UT0)
Table 12-16. UT0 Field Descriptions
Field Description
UTE UTest Enable. This status bit gives indication when UTest is enabled. All bits in UT0, UT1, UT2, UM0, UM1, UM2,
UM3, and UM4 are locked when this bit is 0. This bit is not writeable to a 1, but may be cleared. The reset value
is 0. The method to set this bit is to provide a password, and if the password matches, the UTE bit is set to reflect
the status of enabled, and is enabled until it is cleared by a register write. The UTE password will only be
accepted if MCR[PGM] = 0 and MCR [ERS] = 0 (program and erase are not being requested). UTE can only be
cleared if UT0[AID] = 1, UT0[AIE] and UT0[EIE] = 0. While clearing UTE, writes to set AIE or set EIE will be
ignored. For UTE, the password 0xF9F9_9999 must be written to the UT0 register.
SCBE Single Bit Correction Enable. SBC enables Single Bit Correction results to be observed in MCR[SBC]. Also is
used as an enable for interrupt signals created by the c90fl module (see c90fl Integration Guide). ECC corrections
that occur when SBCE is cleared will not be logged.
0 Single Bit Corrections observation is disabled.
1 Single Bit Correction observation is enabled.
DSI Data Syndrome Input. These bits enable checks of ECC logic by allowing check bits to be input into the ECC
logic and then read out by doing array reads or array integrity checks. The DSI[7:0] correspond to the 8 ECC
check bits on a double word.
MRE Margin Read Enable. MRE combined with MRV enables Factory Margin Reads to be done. Margin reads are only
active during Array Integrity Checks. Normal user reads are not affected by MRE. MRE is not writable if AID is low.
0 Margin reads are not enabled.
1 Margin reads are enabled during Array Integrity Checks.
MRV Margin Read Value. MRV selects the margin level that is being checked. Margin can be checked to an erased
level (MRV = 1) or to a programmed level (MRV = 0). In order for this value to be valid, MRE must also be set.
MRV is not writable if AID is low.
0 Zero’s margin reads are requested.
1 One’s margin reads are requested.
EIE ECC Data Input Enable. EIE enables the input registers (DSI and DAI) to be the source of data for the array. This
is useful in the ECC logic check. If this bit is set, data read through a BIU read request will be from the DSI and
DAI registers when an address match is achieved to the ADR register. EIE is not simultaneously writable to a 1
as UTI is being cleared to a 0.
0 Data read is from the flash array.
1 Data read is from the DSI and DAI registers.